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authorDaniel Sanders <daniel.sanders@imgtec.com>2014-06-12 13:39:06 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2014-06-12 13:39:06 +0000
commit0fa6041625f2b1e263dde8829e265c34dfd79483 (patch)
treebd1f8d0af01135db555cfd201d1747aff6292744 /clang/lib/Frontend/CompilerInstance.cpp
parent15c5784d3ce42afcd5b641532912d3b05d97d36b (diff)
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[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6
Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
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