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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-09 13:02:27 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-09 13:02:27 +0000 |
| commit | f2056bef3246f93ae272cb7322da9618b08f7e05 (patch) | |
| tree | 06b4abc424c4511eca652b8da3b972925ec6cafb /clang/lib/Format/BreakableToken.cpp | |
| parent | 826b5adb6c21ebfded6fa67211d66a6257d3edfd (diff) | |
| download | bcm5719-llvm-f2056bef3246f93ae272cb7322da9618b08f7e05.tar.gz bcm5719-llvm-f2056bef3246f93ae272cb7322da9618b08f7e05.zip | |
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-III that was available in MIPS32
A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.
There's some obvious InstAlias's that ought to be marked MIPS-III but arent.
This is because they are not currently tested. I intend to catch these with
a final pass through the tablegen records to find tablegen records without
ISA annotations.
Depends on D3674
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3675
llvm-svn: 208408
Diffstat (limited to 'clang/lib/Format/BreakableToken.cpp')
0 files changed, 0 insertions, 0 deletions
