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authorJohnny Chen <johnny.chen@apple.com>2009-11-07 00:54:36 +0000
committerJohnny Chen <johnny.chen@apple.com>2009-11-07 00:54:36 +0000
commit3467dcb12de53758e1a6a74ad4e43e56c63f90ca (patch)
tree29a903a3bb29968798af097a0a2d975a35633d53 /clang/lib/CodeGen
parent22053c0f46d803884d90c664aa0df1a9149a0e2c (diff)
downloadbcm5719-llvm-3467dcb12de53758e1a6a74ad4e43e56c63f90ca.tar.gz
bcm5719-llvm-3467dcb12de53758e1a6a74ad4e43e56c63f90ca.zip
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means register/register with no shift, see A8-11. llvm-svn: 86319
Diffstat (limited to 'clang/lib/CodeGen')
0 files changed, 0 insertions, 0 deletions
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