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authorDaniel Sanders <daniel.sanders@imgtec.com>2013-10-17 14:55:58 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2013-10-17 14:55:58 +0000
commit9469417064a14c9c60034ed766ef7087c9d6c0d9 (patch)
treeea0035b80d85ff88a593fd16bd25cf88449ac51b /clang/lib/CodeGen/CodeGenModule.cpp
parent206bf6243c0302dbe86b2e513168144b560e264f (diff)
downloadbcm5719-llvm-9469417064a14c9c60034ed766ef7087c9d6c0d9.tar.gz
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[mips] Added -mfp64 and -mfp32 options.
These options specify 64-bit FP registers and 32-bit FP registers respectively. When using -mfp32, the FPU has 16x double-precision registers overlapping with the 32x single-precision registers (each double-precision register overlaps two single-precision registers). When using -mfp64, the FPU has 32x double-precision registers overlapping with the 32x single-precision registers (each double-precision register overlaps with one single-precision register and has an additional 32-bits). MSA requires -mfp64. llvm-svn: 192899
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