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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-04-03 14:08:13 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-04-03 14:08:13 +0000 |
| commit | 084ff8e891ae0f46fc0cb26a597b251ebd5f49ec (patch) | |
| tree | 942be4ced4256e09b58760de72e0d2798e14fee2 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | a628c98bd3d9f26126917b506e8d13af66e2b9cd (diff) | |
| download | bcm5719-llvm-084ff8e891ae0f46fc0cb26a597b251ebd5f49ec.tar.gz bcm5719-llvm-084ff8e891ae0f46fc0cb26a597b251ebd5f49ec.zip | |
More direct types in PowerPC AltiVec intrinsics.
This patch follows up on work done by Bill Schmidt in r178277,
and replaces most of the remaining uses of VRRC in ISEL DAG patterns.
The resulting .inc files are identical except for comments, so
no change in code generation is expected.
llvm-svn: 178656
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions
