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authorHiroshi Inoue <inouehrs@jp.ibm.com>2017-10-02 09:24:00 +0000
committerHiroshi Inoue <inouehrs@jp.ibm.com>2017-10-02 09:24:00 +0000
commitdcedd66b007f535f0b4be67ec6d186b136d6921b (patch)
tree3731fde675f82c45d1ba71552be35ca73d165a38 /clang/lib/CodeGen/CodeGenFunction.cpp
parentba45584c4b664569adfb445508f5e7010fbf907e (diff)
downloadbcm5719-llvm-dcedd66b007f535f0b4be67ec6d186b136d6921b.tar.gz
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[PowerPC] support ZERO_EXTEND in tryBitPermutation
This patch add a support of ISD::ZERO_EXTEND in PPCDAGToDAGISel::tryBitPermutation to increase the opportunity to use rotate-and-mask by reordering ZEXT and ANDI. Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction. For example, we allow these nodes t9: i32 = add t7, Constant:i32<1> t11: i32 = and t9, Constant:i32<255> t12: i64 = zero_extend t11 t14: i64 = shl t12, Constant:i64<2> to be folded into a rotate-and-mask instruction. Such case often happens in array accesses with logical AND operation in the index, e.g. array[i & 0xFF]; Differential Revision: https://reviews.llvm.org/D37514 llvm-svn: 314655
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