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| author | Craig Topper <craig.topper@intel.com> | 2018-02-02 17:02:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-02 17:02:58 +0000 |
| commit | e538fc74d4c0d30f8c652c3f4e46375339e9d27b (patch) | |
| tree | 7836b5b1bdf0413068d4b82265af3fc9f5e7c6a3 /clang/lib/CodeGen/CGVTT.cpp | |
| parent | c40fdcdd7e8132edb4e4ecff3f6914b5ae956932 (diff) | |
| download | bcm5719-llvm-e538fc74d4c0d30f8c652c3f4e46375339e9d27b.tar.gz bcm5719-llvm-e538fc74d4c0d30f8c652c3f4e46375339e9d27b.zip | |
[X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove mcpu/mattr from assembly test command lines.
Summary:
We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode.
I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features.
Fixes PR36202
Reviewers: RKSimon, echristo, bkramer
Reviewed By: echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42824
llvm-svn: 324106
Diffstat (limited to 'clang/lib/CodeGen/CGVTT.cpp')
0 files changed, 0 insertions, 0 deletions
