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authorJames Molloy <james.molloy@arm.com>2014-05-07 17:41:15 +0000
committerJames Molloy <james.molloy@arm.com>2014-05-07 17:41:15 +0000
commit491cefbe7a7b6d2fd2ea7681d5594db3fd06bbf5 (patch)
treed32d7ef688761a028b72faf94234635b633dc6f3 /clang/lib/CodeGen/CGCall.cpp
parent32908d7a35211015543afb74f5509c056b47c634 (diff)
downloadbcm5719-llvm-491cefbe7a7b6d2fd2ea7681d5594db3fd06bbf5.tar.gz
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When doing int<->ptr coercion for big-endian, calculate the shift amount correctly.
Previously we calculated the shift amount based upon DataLayout::getTypeAllocSizeInBits. This will only work for legal types - types such as i24 that are created as part of structs for bitfields will return "32" from that function. Change to using getTypeSizeInBits. It turns out that AArch64 didn't run across this problem because it always returned [1 x i64] as the type for a bitfield, whereas ARM64 returns i64 so goes down this (better, but wrong) codepath. llvm-svn: 208231
Diffstat (limited to 'clang/lib/CodeGen/CGCall.cpp')
-rw-r--r--clang/lib/CodeGen/CGCall.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index da504739836..972a7c8dbb7 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -700,8 +700,9 @@ static llvm::Value *CoerceIntOrPtrToIntOrPtr(llvm::Value *Val,
if (DL.isBigEndian()) {
// Preserve the high bits on big-endian targets.
// That is what memory coercion does.
- uint64_t SrcSize = DL.getTypeAllocSizeInBits(Val->getType());
- uint64_t DstSize = DL.getTypeAllocSizeInBits(DestIntTy);
+ uint64_t SrcSize = DL.getTypeSizeInBits(Val->getType());
+ uint64_t DstSize = DL.getTypeSizeInBits(DestIntTy);
+
if (SrcSize > DstSize) {
Val = CGF.Builder.CreateLShr(Val, SrcSize - DstSize, "coerce.highbits");
Val = CGF.Builder.CreateTrunc(Val, DestIntTy, "coerce.val.ii");
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