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authorVladimir Sukharev <vladimir.sukharev@arm.com>2015-05-14 08:25:18 +0000
committerVladimir Sukharev <vladimir.sukharev@arm.com>2015-05-14 08:25:18 +0000
commitc6dab75bd4459e53468b5e676dc962c3d88126a0 (patch)
tree4080f18546d88e94c9b095d32b2f7e6012f8b827 /clang/lib/Basic
parent78b8653a84786cd73511d770f3afbc13538af1fe (diff)
downloadbcm5719-llvm-c6dab75bd4459e53468b5e676dc962c3d88126a0.tar.gz
bcm5719-llvm-c6dab75bd4459e53468b5e676dc962c3d88126a0.zip
[ARM] Add v8.1a architecture
Add support for ARMv8.1a architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy, rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8799 llvm-svn: 237349
Diffstat (limited to 'clang/lib/Basic')
-rw-r--r--clang/lib/Basic/Targets.cpp33
1 files changed, 30 insertions, 3 deletions
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index e3527f2ab83..0883816ee32 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -4207,7 +4207,11 @@ public:
} else if (CPU == "cortex-r5" || CPU == "cortex-r7" ||
// Enable the hwdiv extension for all v8a AArch32 cores by
// default.
- ArchName == "armv8a" || ArchName == "armv8" ||
+ // FIXME: Use ARMTargetParser. This would require Triple::arm/thumb
+ // to be recogniseable universally.
+ ArchName == "armv8a.1a" || ArchName == "thumbv8a.1a" || //v8.1a
+ ArchName == "armebv8.1a" || ArchName == "thumbebv8.1a" ||
+ ArchName == "armv8a" || ArchName == "armv8" || //v8a
ArchName == "armebv8a" || ArchName == "armebv8" ||
ArchName == "thumbv8a" || ArchName == "thumbv8" ||
ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
@@ -4290,7 +4294,18 @@ public:
.Default(false);
}
// FIXME: Should we actually have some table instead of these switches?
- static const char *getCPUDefineSuffix(StringRef Name) {
+ const char *getCPUDefineSuffix(StringRef Name) const {
+ // FIXME: Use ARMTargetParser
+ if(Name == "generic") {
+ auto subarch = getTriple().getSubArch();
+ switch (subarch) {
+ case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
+ return "8_1A";
+ default:
+ break;
+ }
+ }
+
return llvm::StringSwitch<const char *>(Name)
.Cases("arm8", "arm810", "4")
.Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
@@ -4320,7 +4335,18 @@ public:
.Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
.Default(nullptr);
}
- static const char *getCPUProfile(StringRef Name) {
+ const char *getCPUProfile(StringRef Name) const {
+ if(Name == "generic") {
+ auto subarch = getTriple().getSubArch();
+ switch (subarch) {
+ case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
+ return "A";
+ default:
+ break;
+ }
+ }
+
+ // FIXME: Use ARMTargetParser
return llvm::StringSwitch<const char *>(Name)
.Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
.Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
@@ -4356,6 +4382,7 @@ public:
// We check both CPUArchVer and ArchName because when only triple is
// specified, the default CPU is arm1136j-s.
return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
+ ArchName.endswith("v8.1a") ||
ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
}
void getTargetDefines(const LangOptions &Opts,
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