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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-11-05 11:21:04 +0300 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-11-07 13:58:51 +0300 |
| commit | a751f557d824c569a96051ea5feef1ff32bb4723 (patch) | |
| tree | b940807b01bcc7fa7c0854c21063657af2416dc7 /clang/lib/Basic | |
| parent | 3552d3e0f7c943c3547c0227ddd80fd4d0732a7e (diff) | |
| download | bcm5719-llvm-a751f557d824c569a96051ea5feef1ff32bb4723.tar.gz bcm5719-llvm-a751f557d824c569a96051ea5feef1ff32bb4723.zip | |
[mips] Set macros for Octeon+ CPU
Diffstat (limited to 'clang/lib/Basic')
| -rw-r--r-- | clang/lib/Basic/Targets/Mips.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp index a08c2318aec..b9ab80df619 100644 --- a/clang/lib/Basic/Targets/Mips.cpp +++ b/clang/lib/Basic/Targets/Mips.cpp @@ -62,7 +62,7 @@ void MipsTargetInfo::fillValidCPUList( unsigned MipsTargetInfo::getISARev() const { return llvm::StringSwitch<unsigned>(getCPU()) .Cases("mips32", "mips64", 1) - .Cases("mips32r2", "mips64r2", "octeon", 2) + .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2) .Cases("mips32r3", "mips64r3", 3) .Cases("mips32r5", "mips64r5", 5) .Cases("mips32r6", "mips64r6", 6) @@ -188,7 +188,10 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); - Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); + if (CPU == "octeon+") + Builder.defineMacro("_MIPS_ARCH_OCTEONP"); + else + Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); if (StringRef(CPU).startswith("octeon")) Builder.defineMacro("__OCTEON__"); |
