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authorStefan Pintilie <stefanp@ca.ibm.com>2019-11-21 13:28:51 -0600
committerStefan Pintilie <stefanp@ca.ibm.com>2019-11-21 13:35:48 -0600
commit5fcf89f77893b4c3367f23dd82b426f783e67cff (patch)
tree512d1f7bb05c89c1c1703e428b824dce4a71e070 /clang/lib/Basic
parentf5759d5dbc441f1fe956757408f46e65611b94e5 (diff)
downloadbcm5719-llvm-5fcf89f77893b4c3367f23dd82b426f783e67cff.tar.gz
bcm5719-llvm-5fcf89f77893b4c3367f23dd82b426f783e67cff.zip
[PowerPC] Add new Future CPU for PowerPC
This patch will add -mcpu=future into clang for PowerPC. A CPU type is required for work that may possibly be enabled for some future Power CPU. The CPU type future will serve that purpose. This patch introduces no new functionality. It is an incremental patch on top of which Power PC work for some future CPU can be done. Differential Revision: https://reviews.llvm.org/D70262
Diffstat (limited to 'clang/lib/Basic')
-rw-r--r--clang/lib/Basic/Targets/PPC.cpp16
-rw-r--r--clang/lib/Basic/Targets/PPC.h14
2 files changed, 27 insertions, 3 deletions
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index baa96e21707..1877d4a5ef7 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -159,6 +159,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
}
if (ArchDefs & ArchDefineE500)
Builder.defineMacro("__NO_LWSYNC__");
+ if (ArchDefs & ArchDefineFuture)
+ Builder.defineMacro("_ARCH_PWR_FUTURE");
if (getTriple().getVendor() == llvm::Triple::BGQ) {
Builder.defineMacro("__bg__");
@@ -319,6 +321,13 @@ bool PPCTargetInfo::initFeatureMap(
.Case("e500", true)
.Default(false);
+ // Future CPU should include all of the features of Power 9 as well as any
+ // additional features (yet to be determined) specific to it.
+ if (CPU == "future") {
+ initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+ addFutureSpecificFeatures(Features);
+ }
+
if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
return false;
@@ -332,6 +341,12 @@ bool PPCTargetInfo::initFeatureMap(
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
+// Add features specific to the "Future" CPU.
+void PPCTargetInfo::addFutureSpecificFeatures(
+ llvm::StringMap<bool> &Features) const {
+ return;
+}
+
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
return llvm::StringSwitch<bool>(Feature)
.Case("powerpc", true)
@@ -466,6 +481,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
{"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"},
{"power8"}, {"pwr8"}, {"power9"}, {"pwr9"}, {"powerpc"},
{"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"}, {"ppc64le"},
+ {"future"}
};
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 847338bbac1..7c7307461f9 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -43,9 +43,10 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
ArchDefinePwr7 = 1 << 11,
ArchDefinePwr8 = 1 << 12,
ArchDefinePwr9 = 1 << 13,
- ArchDefineA2 = 1 << 14,
- ArchDefineA2q = 1 << 15,
- ArchDefineE500 = 1 << 16
+ ArchDefineFuture = 1 << 14,
+ ArchDefineA2 = 1 << 15,
+ ArchDefineA2q = 1 << 16,
+ ArchDefineE500 = 1 << 17
} ArchDefineTypes;
@@ -146,6 +147,11 @@ public:
ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+ .Case("future",
+ ArchDefineFuture | ArchDefinePwr9 | ArchDefinePwr8 |
+ ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
+ ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
+ ArchDefinePpcsq)
.Cases("8548", "e500", ArchDefineE500)
.Default(ArchDefineNone);
}
@@ -166,6 +172,8 @@ public:
StringRef CPU,
const std::vector<std::string> &FeaturesVec) const override;
+ void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
+
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override;
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