diff options
| author | Anna Welker <anna.welker@arm.com> | 2019-11-14 11:56:07 +0000 |
|---|---|---|
| committer | Anna Welker <anna.welker@arm.com> | 2019-11-18 10:07:37 +0000 |
| commit | 2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77 (patch) | |
| tree | 82906c79e07e6f4d89e9c52161d45f62fa4a5068 /clang/lib/Basic | |
| parent | c0f6ad7d1f3ccb9d0b9ce9ef8dfa06409ccf1b3e (diff) | |
| download | bcm5719-llvm-2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77.tar.gz bcm5719-llvm-2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77.zip | |
[ARM] Allocatable Global Register Variables for ARM
Provides support for using r6-r11 as globally scoped
register variables. This requires a -ffixed-rN flag
in order to reserve rN against general allocation.
If for a given GRV declaration the corresponding flag
is not found, or the the register in question is the
target's FP, we fail with a diagnostic.
Differential Revision: https://reviews.llvm.org/D68862
Diffstat (limited to 'clang/lib/Basic')
| -rw-r--r-- | clang/lib/Basic/Targets/ARM.cpp | 32 | ||||
| -rw-r--r-- | clang/lib/Basic/Targets/ARM.h | 3 |
2 files changed, 35 insertions, 0 deletions
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index 437a77afdc9..92e5e26eba3 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -879,6 +879,38 @@ ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { return llvm::makeArrayRef(GCCRegAliases); } +bool ARMTargetInfo::validateGlobalRegisterVariable( + StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const { + bool isValid = llvm::StringSwitch<bool>(RegName) + .Case("r6", true) + .Case("r7", true) + .Case("r8", true) + .Case("r9", true) + .Case("r10", true) + .Case("r11", true) + .Case("sp", true) + .Default(false); + HasSizeMismatch = false; + return isValid; +} + +bool ARMTargetInfo::isRegisterReservedGlobally(StringRef RegName) const { + // The "sp" register does not have a -ffixed-sp option, + // so reserve it unconditionally. + if (RegName.equals("sp")) + return true; + + // reserve rN (N:6-11) registers only if the corresponding + // +reserve-rN feature is found + const std::vector<std::string> &Features = getTargetOpts().Features; + const std::string SearchFeature = "+reserve-" + RegName.str(); + for (const std::string &Feature : Features) { + if (Feature.compare(SearchFeature) == 0) + return true; + } + return false; +} + bool ARMTargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { switch (*Name) { diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h index ce87a626593..90fb20f8f7a 100644 --- a/clang/lib/Basic/Targets/ARM.h +++ b/clang/lib/Basic/Targets/ARM.h @@ -161,6 +161,9 @@ public: ArrayRef<const char *> getGCCRegNames() const override; ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; + bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, + bool &HasSizeMismatch) const override; + bool isRegisterReservedGlobally(StringRef RegName) const override; bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override; std::string convertConstraint(const char *&Constraint) const override; |

