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| author | Gabor Buella <gabor.buella@intel.com> | 2018-05-25 06:34:42 +0000 |
|---|---|---|
| committer | Gabor Buella <gabor.buella@intel.com> | 2018-05-25 06:34:42 +0000 |
| commit | 078bb99a9057c261c172cbb74fc7794e0c601cb7 (patch) | |
| tree | ecc46e560f5df280329fc00680d2581c9ae4779d /clang/lib/Basic | |
| parent | d2f1ab1b1001d0ddf9ab227e1666ec9477e47eb9 (diff) | |
| download | bcm5719-llvm-078bb99a9057c261c172cbb74fc7794e0c601cb7.tar.gz bcm5719-llvm-078bb99a9057c261c172cbb74fc7794e0c601cb7.zip | |
[x86] invpcid intrinsic
An intrinsic for an old instruction, as described in the Intel SDM.
Reviewers: craig.topper, rnk
Reviewed By: craig.topper, rnk
Differential Revision: https://reviews.llvm.org/D47142
llvm-svn: 333256
Diffstat (limited to 'clang/lib/Basic')
| -rw-r--r-- | clang/lib/Basic/Targets/X86.cpp | 7 | ||||
| -rw-r--r-- | clang/lib/Basic/Targets/X86.h | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 1f8de5b599b..43fbdc0329a 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -182,6 +182,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "fma", true); + setFeatureEnabledImpl(Features, "invpcid", true); setFeatureEnabledImpl(Features, "movbe", true); LLVM_FALLTHROUGH; case CK_IvyBridge: @@ -811,6 +812,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasPCONFIG = true; } else if (Feature == "+ptwrite") { HasPTWRITE = true; + } else if (Feature == "+invpcid") { + HasINVPCID = true; } X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) @@ -1173,6 +1176,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__PCONFIG__"); if (HasPTWRITE) Builder.defineMacro("__PTWRITE__"); + if (HasINVPCID) + Builder.defineMacro("__INVPCID__"); // Each case falls through to the previous one here. switch (SSELevel) { @@ -1293,6 +1298,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("fsgsbase", true) .Case("fxsr", true) .Case("gfni", true) + .Case("invpcid", true) .Case("lwp", true) .Case("lzcnt", true) .Case("mmx", true) @@ -1370,6 +1376,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("fsgsbase", HasFSGSBASE) .Case("fxsr", HasFXSR) .Case("gfni", HasGFNI) + .Case("invpcid", HasINVPCID) .Case("lwp", HasLWP) .Case("lzcnt", HasLZCNT) .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h index 2db115cd11e..5b862face9b 100644 --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -106,6 +106,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasMOVDIRI = false; bool HasMOVDIR64B = false; bool HasPTWRITE = false; + bool HasINVPCID = false; protected: /// Enumeration of all of the X86 CPUs supported by Clang. |
