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author | Erich Keane <erich.keane@intel.com> | 2018-09-10 21:12:21 +0000 |
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committer | Erich Keane <erich.keane@intel.com> | 2018-09-10 21:12:21 +0000 |
commit | 75822226917b552ee77f414c20a81373690b6c62 (patch) | |
tree | 5e37c4f612f73152722abeb5ef2a1d9112b99215 /clang/lib/Basic/Targets/X86.cpp | |
parent | 911ddd6db532715f5f09386047e2cb35c012c747 (diff) | |
download | bcm5719-llvm-75822226917b552ee77f414c20a81373690b6c62.tar.gz bcm5719-llvm-75822226917b552ee77f414c20a81373690b6c62.zip |
Move AESNI generation to Skylake and Goldmont
The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Cannon Lake currently listed at
https://ark.intel.com that says "IntelĀ® AES New Instructions" "No".
This matches GCC commit
https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01940.html
[1] https://en.wikipedia.org/wiki/AES_instruction_set
Patch By: thiagomacieira
Differential Revision: https://reviews.llvm.org/D51510
llvm-svn: 341862
Diffstat (limited to 'clang/lib/Basic/Targets/X86.cpp')
-rw-r--r-- | clang/lib/Basic/Targets/X86.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index eaca1811c0f..22a8b1e46a0 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -170,6 +170,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "sgx", true); setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "rtm", true); + setFeatureEnabledImpl(Features, "aes", true); LLVM_FALLTHROUGH; case CK_Broadwell: setFeatureEnabledImpl(Features, "rdseed", true); @@ -196,7 +197,6 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "xsaveopt", true); LLVM_FALLTHROUGH; case CK_Westmere: - setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); LLVM_FALLTHROUGH; case CK_Nehalem: @@ -248,10 +248,10 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "fsgsbase", true); + setFeatureEnabledImpl(Features, "aes", true); LLVM_FALLTHROUGH; case CK_Silvermont: setFeatureEnabledImpl(Features, "rdrnd", true); - setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "sse4.2", true); setFeatureEnabledImpl(Features, "prfchw", true); |