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author | Simon Atanasyan <simon@atanasyan.com> | 2019-11-05 02:21:16 +0300 |
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committer | Simon Atanasyan <simon@atanasyan.com> | 2019-11-07 13:58:50 +0300 |
commit | 3552d3e0f7c943c3547c0227ddd80fd4d0732a7e (patch) | |
tree | 7c04687d5fbaf2f8d4f101fc341fd30659fe90f0 /clang/lib/Basic/Targets/Mips.cpp | |
parent | bf996f761b99108c71efc84688597b7c3c63139e (diff) | |
download | bcm5719-llvm-3552d3e0f7c943c3547c0227ddd80fd4d0732a7e.tar.gz bcm5719-llvm-3552d3e0f7c943c3547c0227ddd80fd4d0732a7e.zip |
[mips] Add `octeon+` to the list of CPUs accepted by the driver
Diffstat (limited to 'clang/lib/Basic/Targets/Mips.cpp')
-rw-r--r-- | clang/lib/Basic/Targets/Mips.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp index 9b35bbcb763..a08c2318aec 100644 --- a/clang/lib/Basic/Targets/Mips.cpp +++ b/clang/lib/Basic/Targets/Mips.cpp @@ -39,6 +39,7 @@ bool MipsTargetInfo::processorSupportsGPR64() const { .Case("mips64r5", true) .Case("mips64r6", true) .Case("octeon", true) + .Case("octeon+", true) .Default(false); return false; } @@ -47,7 +48,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = { {"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"}, {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"}, {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"}, - {"octeon"}, {"p5600"}}; + {"octeon"}, {"octeon+"}, {"p5600"}}; bool MipsTargetInfo::isValidCPUName(StringRef Name) const { return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames); |