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author | Michael Zuckerman <Michael.zuckerman@intel.com> | 2016-10-10 05:45:54 +0000 |
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committer | Michael Zuckerman <Michael.zuckerman@intel.com> | 2016-10-10 05:45:54 +0000 |
commit | fe2b9b4fbf860e3dc7da7705f548bc8d7b6ab9c1 (patch) | |
tree | eddf18b8b623589e2968dbc947a6bc953a931757 /clang/lib/Basic/Targets.cpp | |
parent | ac473034fc771e5f1b4ef0ac405df70ed27412a1 (diff) | |
download | bcm5719-llvm-fe2b9b4fbf860e3dc7da7705f548bc8d7b6ab9c1.tar.gz bcm5719-llvm-fe2b9b4fbf860e3dc7da7705f548bc8d7b6ab9c1.zip |
[x86][inline-asm][clang] accept 'v' constraint
Commit in the name of: Coby Tayree
1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64).
2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent)
This patch applies the needed changes to clang
LLVM patch: https://reviews.llvm.org/D25005
Differential Revision: D25004
llvm-svn: 283716
Diffstat (limited to 'clang/lib/Basic/Targets.cpp')
-rw-r--r-- | clang/lib/Basic/Targets.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 52dd91bce04..5a585981fbb 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -4005,6 +4005,7 @@ X86TargetInfo::validateAsmConstraint(const char *&Name, case 'u': // Second from top of floating point stack. case 'q': // Any register accessible as [r]l: a, b, c, and d. case 'y': // Any MMX register. + case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) case 'x': // Any SSE register. case 'Q': // Any register accessible as [r]h: a, b, c, and d. case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. @@ -4045,6 +4046,7 @@ bool X86TargetInfo::validateOperandSize(StringRef Constraint, case 't': case 'u': return Size <= 128; + case 'v': case 'x': if (SSELevel >= AVX512F) // 512-bit zmm registers can be used if target supports AVX512F. |