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| author | Silviu Baranga <silviu.baranga@arm.com> | 2015-08-19 14:11:27 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2015-08-19 14:11:27 +0000 |
| commit | ad1b19fcb718b1010aaab492e3cab80ab7a71406 (patch) | |
| tree | f466116dfcd807a04d103d33fdc70e70afc1819e /clang/lib/Basic/Targets.cpp | |
| parent | 746da5fe2a407254753965473728ee574d1b906c (diff) | |
| download | bcm5719-llvm-ad1b19fcb718b1010aaab492e3cab80ab7a71406.tar.gz bcm5719-llvm-ad1b19fcb718b1010aaab492e3cab80ab7a71406.zip | |
[ARM] Add instruction selection patterns for vmin/vmax
Summary:
The mid-end was generating vector smin/smax/umin/umax nodes, but
we were using vbsl to generatate the code. This adds the vmin/vmax
patterns and a test to check that we are now generating vmin/vmax
instructions.
Reviewers: rengolin, jmolloy
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D12105
llvm-svn: 245439
Diffstat (limited to 'clang/lib/Basic/Targets.cpp')
0 files changed, 0 insertions, 0 deletions
