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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-11-15 21:51:43 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-11-15 21:51:43 +0000
commit301162c4fe0daa33b53f5e62c713cc9e42696800 (patch)
treeab4a22800fb7c072c9c03166b20b366fe4e2c0ce /clang/lib/AST/Expr.cpp
parentafbe849d7745811b0fc7c67e07be59330f099393 (diff)
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AMDGPU: Replace i64 add/sub lowering
Use VOP3 add/addc like usual. This has some tradeoffs. Inline immediates fold a little better, but other constants are worse off. SIShrinkInstructions could be made smarter to handle these cases. This allows us to avoid selecting scalar adds where we need to track the carry in scc and replace its users. This makes it easier to use the carryless VALU adds. llvm-svn: 318340
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