Generate arm_neon.inc in include/clang/Basic, which provides:

1. builtins definitions for BuiltinsARM.def
2. intrinsic validation code for SemaChecking

Unsure as to whether this is the best way to handle the make dependencies or not.

llvm-svn: 106208

3 files changed, 349 insertions, 214 deletions

diff --git a/clang/include/clang/Basic/BuiltinsARM.def b/clang/include/clang/Basic/BuiltinsARM.def
index 3172e65fef5..54e4c2b2083 100644
--- a/clang/include/clang/Basic/BuiltinsARM.def
+++ b/clang/include/clang/Basic/BuiltinsARM.def
@@ -19,218 +19,8 @@ BUILTIN(__clear_cache, "vc*c*", "")
 BUILTIN(__builtin_thread_pointer, "v*", "")
 
 // NEON
-BUILTIN(__builtin_neon_vaba_v, "V8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vabaq_v, "V16cV16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vabal_v, "V16cV16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vabd_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vabdq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vabdl_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vabs_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vabsq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vaddhn_v, "V8cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vaddl_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vaddw_v, "V16cV16cV8ci", "n")
-BUILTIN(__builtin_neon_vcage_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vcageq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vcagt_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vcagtq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vcale_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vcaleq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vcalt_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vcaltq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vcls_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vclsq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vclz_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vclzq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vcnt_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vcntq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vcvt_f16_v, "V8cV16ci", "n")
-BUILTIN(__builtin_neon_vcvt_f32_v, "V2fV8ci", "n")
-BUILTIN(__builtin_neon_vcvtq_f32_v, "V4fV16ci", "n")
-BUILTIN(__builtin_neon_vcvt_f32_f16, "V16cV8ci", "n")
-BUILTIN(__builtin_neon_vcvt_n_f32_v, "V2fV8cii", "n")
-BUILTIN(__builtin_neon_vcvtq_n_f32_v, "V4fV16cii", "n")
-BUILTIN(__builtin_neon_vcvt_n_s32_v, "V8cV8cii", "n")
-BUILTIN(__builtin_neon_vcvtq_n_s32_v, "V16cV16cii", "n")
-BUILTIN(__builtin_neon_vcvt_n_u32_v, "V8cV8cii", "n")
-BUILTIN(__builtin_neon_vcvtq_n_u32_v, "V16cV16cii", "n")
-BUILTIN(__builtin_neon_vcvt_s32_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vcvtq_s32_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vcvt_u32_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vcvtq_u32_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vext_v, "V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vextq_v, "V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vget_lane_i8, "UcV8ci", "n")
-BUILTIN(__builtin_neon_vget_lane_i16, "UsV4si", "n")
-BUILTIN(__builtin_neon_vget_lane_i32, "UiV2ii", "n")
-BUILTIN(__builtin_neon_vget_lane_f32, "fV2fi", "n")
-BUILTIN(__builtin_neon_vgetq_lane_i8, "UcV16ci", "n")
-BUILTIN(__builtin_neon_vgetq_lane_i16, "UsV8si", "n")
-BUILTIN(__builtin_neon_vgetq_lane_i32, "UiV4ii", "n")
-BUILTIN(__builtin_neon_vgetq_lane_f32, "fV4fi", "n")
-BUILTIN(__builtin_neon_vget_lane_i64, "ULLiV1LLii", "n")
-BUILTIN(__builtin_neon_vgetq_lane_i64, "ULLiV2LLii", "n")
-BUILTIN(__builtin_neon_vhadd_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vhaddq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vhsub_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vhsubq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vld1q_v, "V16cvC*i", "n")
-BUILTIN(__builtin_neon_vld1_v, "V8cvC*i", "n")
-BUILTIN(__builtin_neon_vld1q_dup_v, "V16cvC*i", "n")
-BUILTIN(__builtin_neon_vld1_dup_v, "V8cvC*i", "n")
-BUILTIN(__builtin_neon_vld1q_lane_v, "V16cvC*ii", "n")
-BUILTIN(__builtin_neon_vld1_lane_v, "V8cvC*ii", "n")
-BUILTIN(__builtin_neon_vld2q_v, "V32cvC*i", "n")
-BUILTIN(__builtin_neon_vld2_v, "V16cvC*i", "n")
-BUILTIN(__builtin_neon_vld2_dup_v, "V16cvC*i", "n")
-BUILTIN(__builtin_neon_vld2q_lane_v, "V32cvC*ii", "n")
-BUILTIN(__builtin_neon_vld2_lane_v, "V16cvC*ii", "n")
-BUILTIN(__builtin_neon_vld3q_v, "V48cvC*i", "n")
-BUILTIN(__builtin_neon_vld3_v, "V24cvC*i", "n")
-BUILTIN(__builtin_neon_vld3_dup_v, "V24cvC*i", "n")
-BUILTIN(__builtin_neon_vld3q_lane_v, "V48cvC*ii", "n")
-BUILTIN(__builtin_neon_vld3_lane_v, "V24cvC*ii", "n")
-BUILTIN(__builtin_neon_vld4q_v, "V64cvC*i", "n")
-BUILTIN(__builtin_neon_vld4_v, "V32cvC*i", "n")
-BUILTIN(__builtin_neon_vld4_dup_v, "V32cvC*i", "n")
-BUILTIN(__builtin_neon_vld4q_lane_v, "V64cvC*ii", "n")
-BUILTIN(__builtin_neon_vld4_lane_v, "V32cvC*ii", "n")
-BUILTIN(__builtin_neon_vmax_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vmaxq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vmin_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vminq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vmlal_v, "V16cV16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vmlal_lane_v, "V16cV16cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vmla_lane_v, "V8cV8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vmlaq_lane_v, "V16cV16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vmlsl_v, "V16cV16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vmlsl_lane_v, "V16cV16cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vmls_lane_v, "V8cV8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vmlsq_lane_v, "V16cV16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vmovl_v, "V16cV8ci", "n")
-BUILTIN(__builtin_neon_vmovn_v, "V8cV16ci", "n")
-BUILTIN(__builtin_neon_vmull_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vmull_lane_v, "V16cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vpadal_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vpadalq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vpadd_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vpaddl_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vpaddlq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vpmax_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vpmin_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqabs_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vqabsq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vqadd_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqaddq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vqdmlal_v, "V16cV16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqdmlal_lane_v, "V16cV16cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vqdmlsl_v, "V16cV16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqdmlsl_lane_v, "V16cV16cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vqdmulh_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqdmulhq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vqdmulh_lane_v, "V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vqdmulhq_lane_v, "V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vqdmull_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqdmull_lane_v, "V16cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vqmovn_v, "V8cV16ci", "n")
-BUILTIN(__builtin_neon_vqmovun_v, "V8cV16ci", "n")
-BUILTIN(__builtin_neon_vqneg_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vqnegq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vqrdmulh_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqrdmulhq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vqrdmulh_lane_v, "V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vqrdmulhq_lane_v, "V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vqrshl_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqrshlq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vqrshrn_n_v, "V8cV16cii", "n")
-BUILTIN(__builtin_neon_vqrshrun_n_v, "V8cV16cii", "n")
-BUILTIN(__builtin_neon_vqshl_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqshlq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vqshlu_n_v, "V8cV8cii", "n")
-BUILTIN(__builtin_neon_vqshluq_n_v, "V16cV16cii", "n")
-BUILTIN(__builtin_neon_vqshl_n_v, "V8cV8cii", "n")
-BUILTIN(__builtin_neon_vqshlq_n_v, "V16cV16cii", "n")
-BUILTIN(__builtin_neon_vqshrn_n_v, "V8cV16cii", "n")
-BUILTIN(__builtin_neon_vqshrun_n_v, "V8cV16cii", "n")
-BUILTIN(__builtin_neon_vqsub_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vqsubq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vraddhn_v, "V8cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vrecpe_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vrecpeq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vrecps_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vrecpsq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vrhadd_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vrhaddq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vrshl_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vrshlq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vrshrn_n_v, "V8cV16cii", "n")
-BUILTIN(__builtin_neon_vrshr_n_v, "V8cV8cii", "n")
-BUILTIN(__builtin_neon_vrshrq_n_v, "V16cV16cii", "n")
-BUILTIN(__builtin_neon_vrsqrte_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vrsqrteq_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vrsqrts_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vrsqrtsq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vrsra_n_v, "V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vrsraq_n_v, "V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vrsubhn_v, "V8cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vset_lane_i8, "V8cUcV8ci", "n")
-BUILTIN(__builtin_neon_vset_lane_i16, "V4sUsV4si", "n")
-BUILTIN(__builtin_neon_vset_lane_i32, "V2iUiV2ii", "n")
-BUILTIN(__builtin_neon_vset_lane_f32, "V2ffV2fi", "n")
-BUILTIN(__builtin_neon_vsetq_lane_i8, "V16cUcV16ci", "n")
-BUILTIN(__builtin_neon_vsetq_lane_i16, "V8sUsV8si", "n")
-BUILTIN(__builtin_neon_vsetq_lane_i32, "V4iUiV4ii", "n")
-BUILTIN(__builtin_neon_vsetq_lane_f32, "V4ffV4fi", "n")
-BUILTIN(__builtin_neon_vset_lane_i64, "V1LLiULLiV1LLii", "n")
-BUILTIN(__builtin_neon_vsetq_lane_i64, "V2LLiULLiV2LLii", "n")
-BUILTIN(__builtin_neon_vshl_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vshlq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vshll_n_v, "V16cV8cii", "n")
-BUILTIN(__builtin_neon_vshl_n_v, "V8cV8cii", "n")
-BUILTIN(__builtin_neon_vshlq_n_v, "V16cV16cii", "n")
-BUILTIN(__builtin_neon_vshrn_n_v, "V8cV16cii", "n")
-BUILTIN(__builtin_neon_vshr_n_v, "V8cV8cii", "n")
-BUILTIN(__builtin_neon_vshrq_n_v, "V16cV16cii", "n")
-BUILTIN(__builtin_neon_vsli_n_v, "V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vsliq_n_v, "V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vsra_n_v, "V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vsraq_n_v, "V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vsri_n_v, "V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vsriq_n_v, "V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vst1q_v, "vv*V16ci", "n")
-BUILTIN(__builtin_neon_vst1_v, "vv*V8ci", "n")
-BUILTIN(__builtin_neon_vst1q_lane_v, "vv*V16cii", "n")
-BUILTIN(__builtin_neon_vst1_lane_v, "vv*V8cii", "n")
-BUILTIN(__builtin_neon_vst2q_v, "vv*V16cV16ci", "n")
-BUILTIN(__builtin_neon_vst2_v, "vv*V8cV8ci", "n")
-BUILTIN(__builtin_neon_vst2q_lane_v, "vv*V16cV16cii", "n")
-BUILTIN(__builtin_neon_vst2_lane_v, "vv*V8cV8cii", "n")
-BUILTIN(__builtin_neon_vst3q_v, "vv*V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vst3_v, "vv*V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vst3q_lane_v, "vv*V16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vst3_lane_v, "vv*V8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vst4q_v, "vv*V16cV16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vst4_v, "vv*V8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vst4q_lane_v, "vv*V16cV16cV16cV16cii", "n")
-BUILTIN(__builtin_neon_vst4_lane_v, "vv*V8cV8cV8cV8cii", "n")
-BUILTIN(__builtin_neon_vsubhn_v, "V8cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vsubl_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vsubw_v, "V16cV16cV8ci", "n")
-BUILTIN(__builtin_neon_vtbl1_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtbl2_v, "V8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtbl3_v, "V8cV8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtbl4_v, "V8cV8cV8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtbx1_v, "V8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtbx2_v, "V8cV8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtbx3_v, "V8cV8cV8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtbx4_v, "V8cV8cV8cV8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtrn_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtrnq_v, "V32cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vtst_v, "V8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vtstq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vuzp_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vuzpq_v, "V32cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vzip_v, "V16cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vzipq_v, "V32cV16cV16ci", "n")
+#define GET_NEON_BUILTINS
+#include "clang/Basic/arm_neon.inc"
+#undef GET_NEON_BUILTINS
 
 #undef BUILTIN
diff --git a/clang/include/clang/Basic/Makefile b/clang/include/clang/Basic/Makefile
index a1445ced32e..f01ef10dbe1 100644
--- a/clang/include/clang/Basic/Makefile
+++ b/clang/include/clang/Basic/Makefile
@@ -3,7 +3,7 @@ BUILT_SOURCES = DiagnosticAnalysisKinds.inc DiagnosticASTKinds.inc \
 	DiagnosticCommonKinds.inc DiagnosticDriverKinds.inc \
 	DiagnosticFrontendKinds.inc DiagnosticLexKinds.inc \
 	DiagnosticParseKinds.inc DiagnosticSemaKinds.inc \
-        DiagnosticGroups.inc AttrList.inc
+  DiagnosticGroups.inc AttrList.inc arm_neon.inc
 
 TABLEGEN_INC_FILES_COMMON = 1
 
@@ -23,3 +23,7 @@ $(ObjDir)/AttrList.inc.tmp : Attr.td $(TBLGEN) $(ObjDir)/.dir
 	$(Echo) "Building Clang attribute list with tblgen"
 	$(Verb) $(TableGen) -gen-clang-attr-list -o $(call SYSPATH, $@) \
 	  -I $(PROJ_SRC_DIR)/../.. $<
+
+$(ObjDir)/arm_neon.inc.tmp : arm_neon.td $(TBLGEN) $(ObjDir)/.dir
+	$(Echo) "Building Clang arm_neon.inc with tblgen"
+	$(Verb) $(TableGen) -gen-arm-neon-sema -o $(call SYSPATH, $@) $<
diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td
new file mode 100644
index 00000000000..7ffbfb4a46a
--- /dev/null
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -0,0 +1,341 @@
+//===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//  This file defines the TableGen definitions from which the ARM NEON header
+//  file will be generated.  See ARM document DUI0348B.
+//
+//===----------------------------------------------------------------------===//
+
+class Op;
+
+def OP_NONE  : Op;
+def OP_ADD   : Op;
+def OP_SUB   : Op;
+def OP_MUL   : Op;
+def OP_MLA   : Op;
+def OP_MLS   : Op;
+def OP_MUL_N : Op;
+def OP_MLA_N : Op;
+def OP_MLS_N : Op;
+def OP_EQ    : Op;
+def OP_GE    : Op;
+def OP_LE    : Op;
+def OP_GT    : Op;
+def OP_LT    : Op;
+def OP_NEG   : Op;
+def OP_NOT   : Op;
+def OP_AND   : Op;
+def OP_OR    : Op;
+def OP_XOR   : Op;
+def OP_ANDN  : Op;
+def OP_ORN   : Op;
+def OP_CAST  : Op;
+def OP_HI    : Op;
+def OP_LO    : Op;
+def OP_CONC  : Op;
+def OP_DUP   : Op;
+def OP_SEL   : Op;
+def OP_REV64 : Op;
+def OP_REV32 : Op;
+def OP_REV16 : Op;
+
+class Inst <string p, string t, Op o> {
+  string Prototype = p;
+  string Types = t;
+  Op Operand = o;
+  bit isShift = 0;
+}
+
+// Used to generate Builtins.def
+class SInst<string p, string t> : Inst<p, t, OP_NONE> {}
+class IInst<string p, string t> : Inst<p, t, OP_NONE> {}
+class WInst<string p, string t> : Inst<p, t, OP_NONE> {}
+
+// prototype: return (arg, arg, ...)
+// v: void
+// t: best-fit integer (int/poly args)
+// x: signed integer   (int/float args)
+// u: unsigned integer (int/float args)
+// f: float (int args)
+// d: default
+// w: double width elements, same num elts
+// n: double width elements, half num elts
+// h: half width elements, double num elts
+// e: half width elements, double num elts, unsigned
+// i: constant int
+// l: constant uint64
+// s: scalar of element type
+// a: scalar of element type (splat to vector type)
+// k: default elt width, double num elts
+// #: array of default vectors
+// p: pointer type
+// c: const pointer type
+
+// sizes:
+// c: char
+// s: short
+// i: int
+// l: long
+// f: float
+// h: half-float
+
+// size modifiers:
+// U: unsigned
+// Q: 128b
+// P: polynomial
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.1 Addition
+def VADD    : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
+def VADDL   : SInst<"wdd", "csiUcUsUi">;
+def VADDW   : SInst<"wwd", "csiUcUsUi">;
+def VHADD   : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VRHADD  : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VQADD   : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VADDHN  : IInst<"dww", "csiUcUsUi">;
+def VRADDHN : IInst<"dww", "csiUcUsUi">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.2 Multiplication
+def VMUL     : Inst<"ddd",  "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_MUL>;
+def VMLA     : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
+def VMLAL    : SInst<"wwdd", "csiUcUsUi">;
+def VMLS     : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
+def VMLSL    : SInst<"wwdd", "csiUcUsUi">;
+def VQDMULH  : SInst<"ddd",  "siQsQi">;
+def VQRDMULH : SInst<"ddd",  "siQsQi">;
+def VQDMLAL  : SInst<"wwdd", "si">;
+def VQDMLSL  : SInst<"wwdd", "si">;
+def VMULL    : SInst<"wdd",  "csiUcUsUiPc">;
+def VQDMULL  : SInst<"wdd",  "si">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.3 Subtraction
+def VSUB    : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
+def VSUBL   : SInst<"wdd", "csiUcUsUi">;
+def VSUBW   : SInst<"wwd", "csiUcUsUi">;
+def VQSUB   : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VHSUB   : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VSUBHN  : IInst<"dww", "csiUcUsUi">;
+def VRSUBHN : IInst<"dww", "csiUcUsUi">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.4 Comparison
+def VCEQ  : Inst<"udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
+def VCGE  : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
+def VCLE  : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
+def VCGT  : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
+def VCLT  : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
+def VCAGE : IInst<"udd", "fQf">;
+def VCALE : IInst<"udd", "fQf">;
+def VCAGT : IInst<"udd", "fQf">;
+def VCALT : IInst<"udd", "fQf">;
+def VTST  : WInst<"udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.5 Absolute Difference
+def VABD  : SInst<"ddd",  "csiUcUsUifQcQsQiQUcQUsQUiQf">;
+def VABDL : SInst<"wdd",  "csiUcUsUi">;
+def VABA  : SInst<"dddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VABAL : SInst<"wwdd", "csiUcUsUi">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.6 Max/Min
+def VMAX : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
+def VMIN : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.7 Pairdise Addition
+def VPADD  : IInst<"ddd", "csiUcUsUif">;
+def VPADDL : SInst<"nd",  "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VPADAL : SInst<"nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.8-9 Folding Max/Min
+def VPMAX : SInst<"ddd", "csiUcUsUif">;
+def VPMIN : SInst<"ddd", "csiUcUsUif">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.10 Reciprocal/Sqrt
+def VRECPS  : IInst<"ddd", "fQf">;
+def VRSQRTS : IInst<"ddd", "fQf">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.11 Shifts by signed variable
+def VSHL   : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQSHL  : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VRSHL  : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQRSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.12 Shifts by constant
+let isShift = 1 in {
+def VSHR_N     : SInst<"ddi",  "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VSHL_N     : IInst<"ddi",  "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VRSHR_N    : SInst<"ddi",  "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VSRA_N     : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VRSRA_N    : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQSHL_N    : SInst<"ddi",  "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQSHLU_N   : SInst<"udi",  "csilQcQsQiQl">;
+def VSHRN_N    : IInst<"hki",  "silUsUiUl">;
+def VQSHRUN_N  : SInst<"eki",  "sil">;
+def VQRSHRUN_N : SInst<"eki",  "sil">;
+def VQSHRN_N   : SInst<"hki",  "silUsUiUl">;
+def VRSHRN_N   : IInst<"hki",  "silUsUiUl">;
+def VQRSHRN_N  : SInst<"hki",  "silUsUiUl">;
+def VSHLL_N    : SInst<"wdi",  "csiUcUsUi">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.13 Shifts with insert
+def VSRI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
+def VSLI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.14 Loads and stores of a single vector
+def VLD1      : WInst<"dc",   "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD1_LANE : WInst<"dci",  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD1_DUP  : WInst<"dc",   "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST1      : WInst<"vpd",  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST1_LANE : WInst<"vpdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.15 Loads and stores of an N-element structure
+def VLD2      : WInst<"2c",   "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD3      : WInst<"3c",   "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD4      : WInst<"4c",   "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD2_DUP  : WInst<"2c",   "UcUsUiUlcsilhfPcPs">;
+def VLD3_DUP  : WInst<"3c",   "UcUsUiUlcsilhfPcPs">;
+def VLD4_DUP  : WInst<"4c",   "UcUsUiUlcsilhfPcPs">;
+def VLD2_LANE : WInst<"2ci",  "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VLD3_LANE : WInst<"3ci",  "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VLD4_LANE : WInst<"4ci",  "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VST2      : WInst<"vp2",  "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST3      : WInst<"vp3",  "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST4      : WInst<"vp4",  "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST2_LANE : WInst<"vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VST3_LANE : WInst<"vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VST4_LANE : WInst<"vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.16 Extract lanes from a vector
+def VGET_LANE : IInst<"sdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.17 Set lanes within a vector
+def VSET_LANE : IInst<"dsdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.18 Initialize a vector from bit pattern
+def VCREATE: Inst<"dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.19 Set all lanes to same value
+def VDUP_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
+def VMOV_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.20 Combining vectors
+def VCOMBINE : Inst<"kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.21 Splitting vectors
+def VGET_HIGH : Inst<"dk", "csilhfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW  : Inst<"dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.22 Converting vectors
+def VCVT_S32     : SInst<"xd",  "fQf">;
+def VCVT_U32     : SInst<"ud",  "fQf">;
+def VCVT_F16     : SInst<"hk",  "f">;
+def VCVT_N_S32   : SInst<"xdi", "fQf">;
+def VCVT_N_U32   : SInst<"udi", "fQf">;
+def VCVT_F32     : SInst<"fd",  "iUiQiQUi">;
+def VCVT_F32_F16 : SInst<"kh",  "f">;
+def VCVT_N_F32   : SInst<"fdi", "iUiQiQUi">;
+def VMOVN        : IInst<"hk",  "silUsUiUl">;
+def VMOVL        : SInst<"wd",  "csiUcUsUi">;
+def VQMOVN       : SInst<"hk",  "silUsUiUl">;
+def VQMOVUN      : SInst<"ek",  "sil">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.23-24 Table lookup, Extended table lookup
+def VTBL1 : WInst<"ddt",  "UccPc">;
+def VTBL2 : WInst<"d2t",  "UccPc">;
+def VTBL3 : WInst<"d3t",  "UccPc">;
+def VTBL4 : WInst<"d4t",  "UccPc">;
+def VTBX1 : WInst<"dddt", "UccPc">;
+def VTBX2 : WInst<"dd2t", "UccPc">;
+def VTBX3 : WInst<"dd3t", "UccPc">;
+def VTBX4 : WInst<"dd4t", "UccPc">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.25 Operations with a scalar value
+def VMLA_LANE     : IInst<"ddddi", "siUsUifQsQiQUsQUiQf">;
+def VMLAL_LANE    : SInst<"wwddi", "siUsUi">;
+def VQDMLAL_LANE  : SInst<"wwddi", "si">; 
+def VMLS_LANE     : IInst<"ddddi", "siUsUifQsQiQUsQUiQf">;
+def VMLSL_LANE    : SInst<"wwddi", "siUsUi">;
+def VQDMLSL_LANE  : SInst<"wwddi", "si">;
+def VMUL_N        : Inst<"dds",    "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
+def VMULL_N       : SInst<"wda",   "siUsUi">;
+def VMULL_LANE    : SInst<"wddi",  "siUsUi">;
+def VQDMULL_N     : SInst<"wda",   "si">;
+def VQDMULL_LANE  : SInst<"wddi",  "si">;
+def VQDMULH_N     : SInst<"dda",   "siQsQi">;
+def VQDMULH_LANE  : SInst<"dddi",  "siQsQi">;
+def VQRDMULH_N    : SInst<"dda",   "siQsQi">;
+def VQRDMULH_LANE : SInst<"dddi",  "siQsQi">;
+def VMLA_N        : Inst<"ddda",   "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
+def VMLAL_N       : SInst<"wwda",  "siUsUi">;
+def VQDMLAL_N     : SInst<"wwda",  "si">;
+def VMLS_N        : Inst<"ddds",   "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
+def VMLSL_N       : SInst<"wwda",  "siUsUi">;
+def VQDMLSL_N     : SInst<"wwda",  "si">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.26 Vector Extract
+def VEXT : WInst<"dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.27 Reverse vector elements (sdap endianness)
+def VREV64 : Inst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", OP_REV64>;
+def VREV32 : Inst<"dd", "csUcUsPcQcQsQUcQUsQPc", OP_REV32>;
+def VREV16 : Inst<"dd", "cUcPcQcQUcQPc", OP_REV16>;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.28 Other single operand arithmetic
+def VABS    : SInst<"dd", "csifQcQsQiQf">;
+def VQABS   : SInst<"dd", "csiQcQsQi">;
+def VNEG    : Inst<"dd",  "csifQcQsQiQf", OP_NEG>;
+def VQNEG   : SInst<"dd", "csiQcQsQi">;
+def VCLS    : SInst<"dd", "csiQcQsQi">;
+def VCLZ    : IInst<"dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VCNT    : WInst<"dd", "UccPcQUcQcQPc">;
+def VRECPE  : SInst<"dd", "fUiQfQUi">;
+def VRSQRTE : SInst<"dd", "fUiQfQUi">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.29 Logical operations
+def VMVN : Inst<"dd",    "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
+def VAND : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
+def VORR : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
+def VEOR : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
+def VBIC : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
+def VORN : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
+def VBSL : Inst<"dudd",  "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs", OP_SEL>;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.30 Transposition operations
+def VTRN: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
+def VZIP: WInst<"2dd", "csUcUsfPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
+def VUZP: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
+
+////////////////////////////////////////////////////////////////////////////////
+// E.3.31 Vector reinterpret cast operations