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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-25 19:24:46 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-25 19:24:46 +0000 |
| commit | fd6fd007739c66cf36d1bfe288b4a96f901a32fd (patch) | |
| tree | 60ffa03ecf503a7767baded66ac24d7036361025 /clang/docs/SourceBasedCodeCoverage.rst | |
| parent | fcbd7f64953b04f42dd59f606e45dc8e88a27548 (diff) | |
| download | bcm5719-llvm-fd6fd007739c66cf36d1bfe288b4a96f901a32fd.tar.gz bcm5719-llvm-fd6fd007739c66cf36d1bfe288b4a96f901a32fd.zip | |
AMDGPU: Correct definitions for bitset instructions
These really read and write the result register, so these need a tied
input.
llvm-svn: 354809
Diffstat (limited to 'clang/docs/SourceBasedCodeCoverage.rst')
0 files changed, 0 insertions, 0 deletions
