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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2018-06-13 15:32:46 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2018-06-13 15:32:46 +0000 |
| commit | ffbee7acdcaafad1cddd4cdac060905922f93cfd (patch) | |
| tree | 333e7f45b1d48daeb547b8c766e55e9916d96790 | |
| parent | 7d4929611c6674acdd20c4954c8dd83e1684aeb5 (diff) | |
| download | bcm5719-llvm-ffbee7acdcaafad1cddd4cdac060905922f93cfd.tar.gz bcm5719-llvm-ffbee7acdcaafad1cddd4cdac060905922f93cfd.zip | |
[AMDGPU][MC][GFX8][GFX9] Allow LDS direct reads for BUFFER_LOAD_DWORDX2/X3/X4
See bug 37653: https://bugs.llvm.org/show_bug.cgi?id=37653
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D47885
llvm-svn: 334609
| -rw-r--r-- | llvm/lib/Target/AMDGPU/BUFInstructions.td | 22 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/mubuf.s | 12 |
2 files changed, 31 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 18a885c71b2..7c0b5e9d8f6 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -798,6 +798,22 @@ defm BUFFER_LOAD_DWORDX3 : MUBUF_Pseudo_Loads < defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads < "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load >; + +// This is not described in AMD documentation, +// but 'lds' versions of these opcodes are available +// in at least GFX8+ chips. See Bug 37653. +let SubtargetPredicate = isVI in { +defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads < + "buffer_load_dwordx2", VReg_64, v2i32, null_frag, 0, 1 +>; +defm BUFFER_LOAD_DWORDX3_LDS : MUBUF_Pseudo_Loads < + "buffer_load_dwordx3", VReg_96, untyped, null_frag, 0, 1 +>; +defm BUFFER_LOAD_DWORDX4_LDS : MUBUF_Pseudo_Loads < + "buffer_load_dwordx4", VReg_128, v4i32, null_frag, 0, 1 +>; +} + defm BUFFER_STORE_BYTE : MUBUF_Pseudo_Stores < "buffer_store_byte", VGPR_32, i32, truncstorei8_global >; @@ -1934,9 +1950,9 @@ defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_Lds_vi <0x11>; defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_Lds_vi <0x12>; defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_Lds_vi <0x13>; defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_Lds_vi <0x14>; -defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_vi <0x15>; -defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_vi <0x16>; -defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_vi <0x17>; +defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_Lds_vi <0x15>; +defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_Lds_vi <0x16>; +defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_Lds_vi <0x17>; defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_vi <0x18>; defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x19>; defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_vi <0x1a>; diff --git a/llvm/test/MC/AMDGPU/mubuf.s b/llvm/test/MC/AMDGPU/mubuf.s index fb15a80f5b9..dffd0656144 100644 --- a/llvm/test/MC/AMDGPU/mubuf.s +++ b/llvm/test/MC/AMDGPU/mubuf.s @@ -779,6 +779,18 @@ buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc // NOSICI: error: not a valid operand. // VI: buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc ; encoding: [0x04,0x40,0xf7,0xe0,0x00,0x00,0x01,0x08] +buffer_load_dwordx2 v[1:2], off, s[4:7], s1 lds +// NOSICI: error: instruction not supported on this GPU +// VI: buffer_load_dwordx2 v[1:2], off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x55,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dwordx3 v[0:2], off, s[4:7], s0 offset:4095 lds +// NOSICI: error: instruction not supported on this GPU +// VI: buffer_load_dwordx3 v[0:2], off, s[4:7], s0 offset:4095 lds ; encoding: [0xff,0x0f,0x59,0xe0,0x00,0x00,0x01,0x00] + +buffer_load_dwordx4 v[1:4], off, s[4:7], s1 lds +// NOSICI: error: instruction not supported on this GPU +// VI: buffer_load_dwordx4 v[1:4], off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x5d,0xe0,0x00,0x01,0x01,0x01] + //===----------------------------------------------------------------------===// // Errors handling //===----------------------------------------------------------------------===// |
