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| author | Pablo Barrio <pablo.barrio@arm.com> | 2019-09-30 16:55:10 +0000 |
|---|---|---|
| committer | Pablo Barrio <pablo.barrio@arm.com> | 2019-09-30 16:55:10 +0000 |
| commit | ffac4e860329bccb5782c83e080d89d6d02a8a7a (patch) | |
| tree | b964387158006ddead85b764e752190355295af2 | |
| parent | b1c1095fdc56385b0902a8221723fd4cd224f4be (diff) | |
| download | bcm5719-llvm-ffac4e860329bccb5782c83e080d89d6d02a8a7a.tar.gz bcm5719-llvm-ffac4e860329bccb5782c83e080d89d6d02a8a7a.zip | |
Fix doc for t inline asm constraints for ARM/Thumb
Summary: The constraint goes up to regs d15 and q7, not d16 and q8.
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68090
llvm-svn: 373228
| -rw-r--r-- | llvm/docs/LangRef.rst | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 70f97c25646..2d4c57b7968 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -3862,12 +3862,12 @@ ARM and ARM's Thumb2 mode: as ``r``. - ``h``: In Thumb2 mode, a high 32-bit GPR register (``r8-r15``). In ARM mode, invalid. -- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, - ``d0-d31``, or ``q0-q15``. -- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, - ``d0-d7``, or ``q0-q3``. -- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or - ``q0-q8``. +- ``w``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d31``, or ``q0-q15``, respectively. +- ``t``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d15``, or ``q0-q7``, respectively. +- ``x``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s15``, ``d0-d7``, or ``q0-q3``, respectively. ARM's Thumb1 mode: @@ -3882,12 +3882,12 @@ ARM's Thumb1 mode: - ``r``: A low 32-bit GPR register (``r0-r7``). - ``l``: A low 32-bit GPR register (``r0-r7``). - ``h``: A high GPR register (``r0-r7``). -- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, - ``d0-d31``, or ``q0-q15``. -- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, - ``d0-d7``, or ``q0-q3``. -- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or - ``q0-q8``. +- ``w``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d31``, or ``q0-q15``, respectively. +- ``t``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d15``, or ``q0-q7``, respectively. +- ``x``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s15``, ``d0-d7``, or ``q0-q3``, respectively. Hexagon: |
