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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-20 21:22:28 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-20 21:22:28 +0000 |
| commit | ff1fbda4cd7af9c0d7f1518cff3dee4e2f6bb1fe (patch) | |
| tree | 530eedefbf4d5fce9a9e2f3edc27d60b6a90210f | |
| parent | 47249631122d85fc85be4fb56330d9901482c017 (diff) | |
| download | bcm5719-llvm-ff1fbda4cd7af9c0d7f1518cff3dee4e2f6bb1fe.tar.gz bcm5719-llvm-ff1fbda4cd7af9c0d7f1518cff3dee4e2f6bb1fe.zip | |
[mips] MUL should clobber HI0 and LO0.
I cannot think of a test case that reliably triggers this bug.
llvm-svn: 191109
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 4795969175a..be6d7532a6c 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -878,6 +878,7 @@ def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>, ADD_FM<0, 0x21>; def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>, ADD_FM<0, 0x23>; +let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; |
