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| author | Craig Topper <craig.topper@intel.com> | 2017-09-28 16:56:36 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-28 16:56:36 +0000 |
| commit | fd6b8a67fb9e0d5d142e9e2cff5e8c944dc864f3 (patch) | |
| tree | 225de90a261684892c7ab81422b9302308b2bad6 | |
| parent | 71a8cf9f991eb75eb12df76240e68030466d4b1e (diff) | |
| download | bcm5719-llvm-fd6b8a67fb9e0d5d142e9e2cff5e8c944dc864f3.tar.gz bcm5719-llvm-fd6b8a67fb9e0d5d142e9e2cff5e8c944dc864f3.zip | |
[X86] Remove dead code from X86ISelDAGToDAG.cpp multiply handling
Summary:
Lowering never creates X86ISD::UMUL for 8-bit types. X86ISD::UMUL8 is used instead. If X86ISD::UMUL 8-bit were ever used it would crash.
DAGCombiner replaces UMUL_LOHI/SMUL_LOHI with a wider MUL and a shift if the type twice as wide is legal. So we should never see i8 UMUL_LOHI/SMUL_LOHI. In fact I think there was a bug in part of the i8 code. Similar is true for i16 though without the bug.
Reviewers: RKSimon, spatel, zvi
Reviewed By: zvi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38276
llvm-svn: 314430
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 250d250af35..84b1f9624ad 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -2594,7 +2594,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) { unsigned LoReg; switch (NVT.SimpleTy) { default: llvm_unreachable("Unsupported VT!"); - case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; + // MVT::i8 is handled by X86ISD::UMUL8. case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; |
