summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorCraig Topper <craig.topper@intel.com>2018-01-24 05:14:33 +0000
committerCraig Topper <craig.topper@intel.com>2018-01-24 05:14:33 +0000
commitfd68c2d0ae8a8b507a28427607be89d216bf08cd (patch)
tree07234f24662739d8f3e32bdaa745bb460b4a891e
parent501931b117981d4ae8ba6cb1edbd1780b3208b92 (diff)
downloadbcm5719-llvm-fd68c2d0ae8a8b507a28427607be89d216bf08cd.tar.gz
bcm5719-llvm-fd68c2d0ae8a8b507a28427607be89d216bf08cd.zip
[X86] Remove redundant regular expression from the Znver1 scheduler model. NFC
llvm-svn: 323303
-rw-r--r--llvm/lib/Target/X86/X86ScheduleZnver1.td1
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 52bf94e68c9..e295f175519 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -1383,7 +1383,6 @@ def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "(V?)CVT(T?)PD2DQrm")>;
def : InstRW<[ZnWriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>;
// x,m256.
def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
-def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQ(64)?rm")>;
def ZnWriteCVTPS2PIr: SchedWriteRes<[ZnFPU3]> {
let Latency = 4;
OpenPOWER on IntegriCloud