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author | Igor Breger <igor.breger@intel.com> | 2016-04-25 08:30:28 +0000 |
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committer | Igor Breger <igor.breger@intel.com> | 2016-04-25 08:30:28 +0000 |
commit | fd63b80486e7116fa133ebfa20fb4ace84d68a90 (patch) | |
tree | c82b2115abe0e30e5af9aff5deb448c1167ac142 | |
parent | ab9390664ff9a70def8ca3efb24fa2aca1874c7a (diff) | |
download | bcm5719-llvm-fd63b80486e7116fa133ebfa20fb4ace84d68a90.tar.gz bcm5719-llvm-fd63b80486e7116fa133ebfa20fb4ace84d68a90.zip |
fix comments
related to
Differential Revision: http://reviews.llvm.org/D17913
llvm-svn: 267383
-rw-r--r-- | llvm/include/llvm/Analysis/TargetTransformInfo.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 36cb6c92241..e566e2a94d6 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -326,8 +326,7 @@ public: unsigned AddrSpace = 0) const; /// \brief Return true if the target supports masked load/store - /// AVX2 and AVX-512 targets allow masks for consecutive load and store for - /// 32 and 64 bit elements. + /// AVX2 and AVX-512 targets allow masks for consecutive load and store bool isLegalMaskedStore(Type *DataType) const; bool isLegalMaskedLoad(Type *DataType) const; |