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| author | Misha Brukman <brukman+llvm@gmail.com> | 2003-06-05 23:30:27 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2003-06-05 23:30:27 +0000 |
| commit | fd394b766a7cecb757771e51f64e06a455ce25e8 (patch) | |
| tree | 9eda688f4083b3bb2be7748b9574f0310cdd3a6b | |
| parent | 1cca1c68e134ced13062a4d2e725ed7c91f7946c (diff) | |
| download | bcm5719-llvm-fd394b766a7cecb757771e51f64e06a455ce25e8.tar.gz bcm5719-llvm-fd394b766a7cecb757771e51f64e06a455ce25e8.zip | |
Do not preset the cc register, the instructions actually use it.
llvm-svn: 6637
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcV9.td | 37 |
1 files changed, 17 insertions, 20 deletions
diff --git a/llvm/lib/Target/Sparc/SparcV9.td b/llvm/lib/Target/Sparc/SparcV9.td index 6c3aa567df2..1d9c4b8fe88 100644 --- a/llvm/lib/Target/Sparc/SparcV9.td +++ b/llvm/lib/Target/Sparc/SparcV9.td @@ -77,27 +77,24 @@ set isDeprecated = 1 in { } #endif -// These instructions are hacked to really represent A.5 instructions, -// but with cc hardcoded to be %fcc0. Hence, they behave like FBPfcc instrs. +// We now make these same opcodes represent the FBPfcc instructions set op2 = 0b101 in { - set cc = 0b00 in { - def FBA : F2_3<0b1000, "fba">; // Branch always - def FBN : F2_3<0b0000, "fbn">; // Branch never - def FBU : F2_3<0b0111, "fbu">; // Branch on unordered - def FBG : F2_3<0b0110, "fbg">; // Branch > - def FBUG : F2_3<0b0101, "fbug">; // Branch on unordered or > - def FBL : F2_3<0b0100, "fbl">; // Branch < - def FBUL : F2_3<0b0011, "fbul">; // Branch on unordered or < - def FBLG : F2_3<0b0010, "fblg">; // Branch < or > - def FBNE : F2_3<0b0001, "fbne">; // Branch != - def FBE : F2_3<0b1001, "fbe">; // Branch == - def FBUE : F2_3<0b1010, "fbue">; // Branch on unordered or == - def FBGE : F2_3<0b1011, "fbge">; // Branch > or == - def FBUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or == - def FBLE : F2_3<0b1101, "fble">; // Branch < or == - def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or == - def FBO : F2_3<0b1111, "fbo">; // Branch on ordered - } + def FBA : F2_3<0b1000, "fba">; // Branch always + def FBN : F2_3<0b0000, "fbn">; // Branch never + def FBU : F2_3<0b0111, "fbu">; // Branch on unordered + def FBG : F2_3<0b0110, "fbg">; // Branch > + def FBUG : F2_3<0b0101, "fbug">; // Branch on unordered or > + def FBL : F2_3<0b0100, "fbl">; // Branch < + def FBUL : F2_3<0b0011, "fbul">; // Branch on unordered or < + def FBLG : F2_3<0b0010, "fblg">; // Branch < or > + def FBNE : F2_3<0b0001, "fbne">; // Branch != + def FBE : F2_3<0b1001, "fbe">; // Branch == + def FBUE : F2_3<0b1010, "fbue">; // Branch on unordered or == + def FBGE : F2_3<0b1011, "fbge">; // Branch > or == + def FBUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or == + def FBLE : F2_3<0b1101, "fble">; // Branch < or == + def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or == + def FBO : F2_3<0b1111, "fbo">; // Branch on ordered } // Section A.5: Branch on FP condition codes with prediction - p143 |
