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authorChad Rosier <mcrosier@apple.com>2011-12-14 17:32:02 +0000
committerChad Rosier <mcrosier@apple.com>2011-12-14 17:32:02 +0000
commitfce28914ea18fc65fc2bd8016d10ae80f8527804 (patch)
treea5e23c286b92bb0187f0bf5ac048bd6b52590ff0
parenta342667fd08a8c9fa8abc9a6002c13dad5777c63 (diff)
downloadbcm5719-llvm-fce28914ea18fc65fc2bd8016d10ae80f8527804.tar.gz
bcm5719-llvm-fce28914ea18fc65fc2bd8016d10ae80f8527804.zip
Tidy up.
llvm-svn: 146568
-rw-r--r--llvm/lib/Target/ARM/ARMFastISel.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index bfeac47811e..df973a7f0fa 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -1130,7 +1130,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
break;
case MVT::f32:
if (!Subtarget->hasVFP2()) return false;
- StrOpc = ARM::VSTRS;
// Unaligned stores need special handling. Floats require word-alignment.
if (Alignment && Alignment < 4) {
unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
@@ -1140,6 +1139,8 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
SrcReg = MoveReg;
VT = MVT::i32;
StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
+ } else {
+ StrOpc = ARM::VSTRS;
}
break;
case MVT::f64:
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