[fast-isel] Add support for returning non-legal types with no sign- or zero-

entend flag.

llvm-svn: 150774

2 files changed, 15 insertions, 6 deletions

diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 21c1f86442e..51c44d0adb0 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2037,14 +2037,14 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
         return false;
 
-      if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
-        return false;
-
       assert(DestVT == MVT::i32 && "ARM should always ext to i32");
 
-      bool isZExt = Outs[0].Flags.isZExt();
-      SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, isZExt);
-      if (SrcReg == 0) return false;
+      // Perform extension if flagged as either zext or sext.  Otherwise, do
+      // nothing.
+      if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
+        SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
+        if (SrcReg == 0) return false;
+      }
     }
 
     // Make the copy.
diff --git a/llvm/test/CodeGen/ARM/fast-isel-ret.ll b/llvm/test/CodeGen/ARM/fast-isel-ret.ll
index 175cd9034ce..689b169ee32 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-ret.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-ret.ll
@@ -46,3 +46,12 @@ entry:
 ; CHECK: bx lr
   ret i16 %a
 }
+
+define i16 @ret6(i16 %a) nounwind uwtable ssp {
+entry:
+; CHECK: ret6
+; CHECK-NOT: uxth
+; CHECK-NOT: sxth
+; CHECK: bx lr
+  ret i16 %a
+}