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| author | Diana Picus <diana.picus@linaro.org> | 2017-02-02 13:20:49 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-02-02 13:20:49 +0000 |
| commit | fc19a8ff07a1c9c57b2b086512d9aaae474bf0f8 (patch) | |
| tree | a2e750675ba290b474c019e757f609e6372d3a81 | |
| parent | aa78ad5fea0d38f51756031ef991b78d2ae0bfaa (diff) | |
| download | bcm5719-llvm-fc19a8ff07a1c9c57b2b086512d9aaae474bf0f8.tar.gz bcm5719-llvm-fc19a8ff07a1c9c57b2b086512d9aaae474bf0f8.zip | |
[ARM] GlobalISel: Legalize loading pointers
Make it legal to load pointer values. Also check that pointers are assigned
to the GPR reg bank by default.
llvm-svn: 293886
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 34 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 3 |
3 files changed, 38 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index f12a4f70251..d1276df57b1 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -35,7 +35,7 @@ ARMLegalizerInfo::ARMLegalizerInfo() { setAction({G_FRAME_INDEX, p0}, Legal); - for (auto Ty : {s1, s8, s16, s32}) + for (auto Ty : {s1, s8, s16, s32, p0}) setAction({G_LOAD, Ty}, Legal); setAction({G_LOAD, 1, p0}, Legal); diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir index d1e8ec3d188..249a0b03795 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -8,6 +8,7 @@ define void @test_add_s32() { ret void } define void @test_load_from_stack() { ret void } + define void @test_legal_loads() { ret void } ... --- name: test_sext_s8 @@ -156,3 +157,36 @@ body: | %1(s32) = G_LOAD %0(p0) BX_RET 14, _ ... +--- +name: test_legal_loads +# CHECK-LABEL: name: test_legal_loads +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; These are all legal, so we should find them unchanged in the output + ; CHECK-DAG: {{%[0-9]+}}(s32) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}(s16) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}(s8) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0 + %0(p0) = COPY %r0 + %1(s32) = G_LOAD %0(p0) + %2(s16) = G_LOAD %0(p0) + %3(s8) = G_LOAD %0(p0) + %4(s1) = G_LOAD %0(p0) + %5(p0) = G_LOAD %0(p0) + BX_RET 14, _ +... diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index d520750ba30..ba6880f3e43 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -123,6 +123,7 @@ selected: false # CHECK: - { id: 2, class: gprb } # CHECK: - { id: 3, class: gprb } # CHECK: - { id: 4, class: gprb } +# CHECK: - { id: 5, class: gprb } registers: - { id: 0, class: _ } @@ -130,6 +131,7 @@ registers: - { id: 2, class: _ } - { id: 3, class: _ } - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0 @@ -138,6 +140,7 @@ body: | %2(s16) = G_LOAD %0 %3(s8) = G_LOAD %0 %4(s1) = G_LOAD %0 + %5(p0) = G_LOAD %0 BX_RET 14, _, implicit %r0 ... |
