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| author | Cameron Zwarich <zwarich@apple.com> | 2011-04-12 02:24:17 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-04-12 02:24:17 +0000 |
| commit | fbcd69b96a891406d304b1a26aea8c5e42660783 (patch) | |
| tree | 9cad4998946a07c85c777248379ff362c0092c62 | |
| parent | 3f28443a07ed5dff324cca0b5c3755058042e621 (diff) | |
| download | bcm5719-llvm-fbcd69b96a891406d304b1a26aea8c5e42660783.tar.gz bcm5719-llvm-fbcd69b96a891406d304b1a26aea8c5e42660783.zip | |
Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.
llvm-svn: 129345
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 24 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fp-arg-shuffle.ll | 2 |
2 files changed, 23 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 330a7816f5c..563b37e6cba 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5684,8 +5684,28 @@ static SDValue PerformSTORECombine(SDNode *N, // Otherwise, the i64 value will be legalized to a pair of i32 values. StoreSDNode *St = cast<StoreSDNode>(N); SDValue StVal = St->getValue(); - if (!ISD::isNormalStore(St) || St->isVolatile() || - StVal.getValueType() != MVT::i64 || + if (!ISD::isNormalStore(St) || St->isVolatile()) + return SDValue(); + + if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && + StVal.getNode()->hasOneUse() && !St->isVolatile()) { + SelectionDAG &DAG = DCI.DAG; + DebugLoc DL = St->getDebugLoc(); + SDValue BasePtr = St->getBasePtr(); + SDValue NewST1 = DAG.getStore(St->getChain(), DL, + StVal.getNode()->getOperand(0), BasePtr, + St->getPointerInfo(), St->isVolatile(), + St->isNonTemporal(), St->getAlignment()); + + SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, + DAG.getConstant(4, MVT::i32)); + return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), + OffsetPtr, St->getPointerInfo(), St->isVolatile(), + St->isNonTemporal(), + std::min(4U, St->getAlignment() / 2)); + } + + if (StVal.getValueType() != MVT::i64 || StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) return SDValue(); diff --git a/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll b/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll index 59303ac06da..ae02b792e4d 100644 --- a/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll +++ b/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -float-abi=soft | FileCheck %s ; CHECK: function1 -; CHECK-NOT: vmov r +; CHECK-NOT: vmov define double @function1(double %a, double %b, double %c, double %d, double %e, double %f) nounwind noinline ssp { entry: %call = tail call double @function2(double %f, double %e, double %d, double %c, double %b, double %a) nounwind |
