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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-02-09 01:14:44 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-02-09 01:14:44 +0000 |
| commit | fb7b14f70d33225a8299db98bff6e99d79f13ae7 (patch) | |
| tree | 3f4b3ce4ba2abf5581a9a56f06f470156d4b0e5f | |
| parent | 79c3255fe4fc61d8b05f3d2993eb807fef8f2cff (diff) | |
| download | bcm5719-llvm-fb7b14f70d33225a8299db98bff6e99d79f13ae7.tar.gz bcm5719-llvm-fb7b14f70d33225a8299db98bff6e99d79f13ae7.zip | |
[CodeGen] Unify the syntax of MBB liveins in MIR and -debug output
Instead of:
Live Ins: %r0 %r1
print:
liveins: %r0, %r1
llvm-svn: 324694
| -rw-r--r-- | llvm/lib/CodeGen/MachineBasicBlock.cpp | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir | 12 |
3 files changed, 20 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 76ed383ac3f..72cc47da7c5 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -323,18 +323,25 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << ":\n"; const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); - if (!livein_empty()) { + const MachineRegisterInfo &MRI = MF->getRegInfo(); + if (!livein_empty() && MRI.tracksLiveness()) { if (Indexes) OS << '\t'; - OS << " Live Ins:"; - for (const auto &LI : LiveIns) { - OS << ' ' << printReg(LI.PhysReg, TRI); + OS.indent(2) << "liveins: "; + + bool First = true; + for (const auto &LI : liveins()) { + if (!First) + OS << ", "; + First = false; + OS << printReg(LI.PhysReg, TRI); if (!LI.LaneMask.all()) - OS << ':' << PrintLaneMask(LI.LaneMask); + OS << ":0x" << PrintLaneMask(LI.LaneMask); } OS << '\n'; } if (!succ_empty()) { + if (Indexes) OS << '\t'; // Print the successors OS.indent(2) << "successors: "; for (auto I = succ_begin(), E = succ_end(); I != E; ++I) { diff --git a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp index 32d801b13de..347f66d1709 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp @@ -60,7 +60,7 @@ namespace llvm { /// expands to the following machine code: /// /// %bb.0: derived from LLVM BB %entry -/// Live Ins: %f1 %f3 %x6 +/// liveins: %f1 %f3 %x6 /// <SNIP1> /// %0 = COPY %f1; F8RC:%0 /// %5 = CMPLWI killed %4, 0; CRRC:%5 GPRC:%4 @@ -98,7 +98,7 @@ namespace llvm { /// If all conditions are meet, IR should collapse to: /// /// %bb.0: derived from LLVM BB %entry -/// Live Ins: %f1 %f3 %x6 +/// liveins: %f1 %f3 %x6 /// <SNIP1> /// %0 = COPY %f1; F8RC:%0 /// %5 = CMPLWI killed %4, 0; CRRC:%5 GPRC:%4 diff --git a/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir b/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir index 508f47d57a4..ab4329fdd6d 100644 --- a/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir +++ b/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir @@ -12,13 +12,13 @@ # implicit use of r0: # # %bb.0: -# Live Ins: %R0 -# %R1 = A2_sxth killed %R0 ; hoisted, kills r0 +# liveins: %r0 +# %r1 = A2_sxth killed %r0 ; hoisted, kills r0 # A2_nop implicit-def %P0 -# %R0 = C2_cmoveit %P0, 2, implicit %R0 ; predicated A2_tfrsi -# %R0 = C2_cmoveif killed %P0, 1, implicit %R0 ; predicated A2_tfrsi -# %R0 = A2_add killed %R0, killed %R1 -# J2_jumpr %R31, implicit dead %PC +# %r0 = C2_cmoveit %P0, 2, implicit %r0 ; predicated A2_tfrsi +# %r0 = C2_cmoveif killed %P0, 1, implicit %r0 ; predicated A2_tfrsi +# %r0 = A2_add killed %r0, killed %r1 +# J2_jumpr %r31, implicit dead %PC # # CHECK: $r1 = A2_sxth killed $r0 |
