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author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-02 11:41:09 +0000 |
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committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-02 11:41:09 +0000 |
commit | faf8e9f8c65a4ad8577189688dd373f124f7052f (patch) | |
tree | 90cc7b314e0006b005fb9ff4d26880a59d27668a | |
parent | f49ab9af2c776465291db05a7b29b1b7f0f00241 (diff) | |
download | bcm5719-llvm-faf8e9f8c65a4ad8577189688dd373f124f7052f.tar.gz bcm5719-llvm-faf8e9f8c65a4ad8577189688dd373f124f7052f.zip |
[GlobalISel] Don't legalize non-generic instructions.
They don't have types and should be legal.
llvm-svn: 277446
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineLegalizePass.cpp | 6 | ||||
-rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir | 36 |
2 files changed, 42 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizePass.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizePass.cpp index 0b8264f613d..bf5025201ba 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizePass.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizePass.cpp @@ -54,6 +54,12 @@ bool MachineLegalizePass::runOnMachineFunction(MachineFunction &MF) { // Get the next Instruction before we try to legalize, because there's a // good chance MI will be deleted. NextMI = std::next(MI); + + // Only legalize pre-isel generic instructions: others don't have types + // and are assumed to be legal. + if (!isPreISelGenericOpcode(MI->getOpcode())) + continue; + auto Res = Helper.legalizeInstr(*MI, Legalizer); // Error out if we couldn't legalize this instruction. We may want to fall diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir new file mode 100644 index 00000000000..d9ff51bc19b --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir @@ -0,0 +1,36 @@ +# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - | FileCheck %s +# REQUIRES: global-isel + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_copy() { ret void } + define void @test_targetspecific() { ret void } +... + +--- +name: test_copy +isSSA: true +registers: + - { id: 0, class: _ } +body: | + bb.0: + liveins: %x0 + ; CHECK-LABEL: name: test_copy + ; CHECK: %0(64) = COPY %x0 + ; CHECK-NEXT: %x0 = COPY %0 + + %0(64) = COPY %x0 + %x0 = COPY %0 +... + +--- +name: test_targetspecific +isSSA: true +body: | + bb.0: + ; CHECK-LABEL: name: test_targetspecific + ; CHECK: RET_ReallyLR + + RET_ReallyLR +... |