Disallow i64 div/rem in PPC32 counter loops

On PPC32, [su]div,rem on i64 types are transformed into runtime library
function calls. As a result, they are not allowed in counter-based loops (the
counter-loops verification pass caught this error; this change fixes PR16169).

llvm-svn: 183581

2 files changed, 100 insertions, 0 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
index d2dd848cafa..08247c289f3 100644
--- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -338,6 +338,13 @@ bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicBlock *BB) {
             CI->getDestTy()->getScalarType()->isIntegerTy(64))
           ))
         return true;
+    } else if (TT.isArch32Bit() &&
+               J->getType()->getScalarType()->isIntegerTy(64) &&
+               (J->getOpcode() == Instruction::UDiv ||
+                J->getOpcode() == Instruction::SDiv ||
+                J->getOpcode() == Instruction::URem ||
+                J->getOpcode() == Instruction::SRem)) {
+      return true;
     } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) {
       // On PowerPC, indirect jumps use the counter register.
       return true;
diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-i64.ll b/llvm/test/CodeGen/PowerPC/ctrloop-i64.ll
new file mode 100644
index 00000000000..9e01392a458
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ctrloop-i64.ll
@@ -0,0 +1,93 @@
+; RUN: llc < %s -mcpu=ppc | FileCheck %s
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
+target triple = "powerpc-unknown-linux-gnu"
+
+define i64 @foo(i64* nocapture %n, i64 %d) nounwind readonly {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
+  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
+  %0 = load i64* %arrayidx, align 8
+  %conv = udiv i64 %x.05, %d
+  %conv1 = add i64 %conv, %0
+  %inc = add nsw i32 %i.06, 1
+  %exitcond = icmp eq i32 %inc, 2048
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i64 %conv1
+}
+
+; CHECK: @foo
+; CHECK-NOT: mtctr
+
+define i64 @foo2(i64* nocapture %n, i64 %d) nounwind readonly {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
+  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
+  %0 = load i64* %arrayidx, align 8
+  %conv = sdiv i64 %x.05, %d
+  %conv1 = add i64 %conv, %0
+  %inc = add nsw i32 %i.06, 1
+  %exitcond = icmp eq i32 %inc, 2048
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i64 %conv1
+}
+
+; CHECK: @foo2
+; CHECK-NOT: mtctr
+
+define i64 @foo3(i64* nocapture %n, i64 %d) nounwind readonly {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
+  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
+  %0 = load i64* %arrayidx, align 8
+  %conv = urem i64 %x.05, %d
+  %conv1 = add i64 %conv, %0
+  %inc = add nsw i32 %i.06, 1
+  %exitcond = icmp eq i32 %inc, 2048
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i64 %conv1
+}
+
+; CHECK: @foo3
+; CHECK-NOT: mtctr
+
+define i64 @foo4(i64* nocapture %n, i64 %d) nounwind readonly {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
+  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
+  %0 = load i64* %arrayidx, align 8
+  %conv = srem i64 %x.05, %d
+  %conv1 = add i64 %conv, %0
+  %inc = add nsw i32 %i.06, 1
+  %exitcond = icmp eq i32 %inc, 2048
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i64 %conv1
+}
+
+; CHECK: @foo4
+; CHECK-NOT: mtctr
+