diff options
| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-05-29 08:15:37 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-05-29 08:15:37 +0000 |
| commit | fa213f797b5c0a0e88cc773ed175a2e594461185 (patch) | |
| tree | dfbcf82b619b691068cce89b94b374d9e25f2acf | |
| parent | df55620c3e2750840cc6aec8fe78eeefc84c58d2 (diff) | |
| download | bcm5719-llvm-fa213f797b5c0a0e88cc773ed175a2e594461185.tar.gz bcm5719-llvm-fa213f797b5c0a0e88cc773ed175a2e594461185.zip | |
[AMDGPU] Fixed build warning
Summary:
V2: Use cast instead of extra if.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D47426
Change-Id: I6ac31da0306f79706960284a7ebd7b9c6237a83a
llvm-svn: 333397
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 13f98b7f87e..a7e773b3f1d 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3601,10 +3601,9 @@ SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode, // Change from v4f16/v2f16 to EquivLoadVT. SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other); - SDValue Load - = DAG.getMemIntrinsicNode(IsIntrinsic ? ISD::INTRINSIC_W_CHAIN : Opcode, DL, - VTList, Ops, M->getMemoryVT(), - M->getMemOperand()); + SDValue Load = DAG.getMemIntrinsicNode( + IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, + DL, VTList, Ops, M->getMemoryVT(), M->getMemOperand()); SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked); |
