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authorVikram S. Adve <vadve@cs.uiuc.edu>2003-07-02 01:16:01 +0000
committerVikram S. Adve <vadve@cs.uiuc.edu>2003-07-02 01:16:01 +0000
commitfa1dde06aaaee7acde52364aa601ae0807445e19 (patch)
treebb90810dafdda46320c66bdbe044901631c769a6
parentb5f8ada255168d1dd908203be48a139d0d4f381a (diff)
downloadbcm5719-llvm-fa1dde06aaaee7acde52364aa601ae0807445e19.tar.gz
bcm5719-llvm-fa1dde06aaaee7acde52364aa601ae0807445e19.zip
A def. operand of a machine instruction may be an ordinary Value*,
not just an Instruction*, at least in one unfortunate case: the first operand to the va_arg instruction. Modify ValueToDefVecMap to map from Value*, not Instruction*. llvm-svn: 7052
-rw-r--r--llvm/lib/CodeGen/InstrSched/SchedGraph.cpp25
1 files changed, 12 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp b/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
index 51fca9d9d87..899e188dab4 100644
--- a/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -34,9 +34,9 @@ struct RegToRefVecMap: public hash_map<int, RefVec> {
typedef hash_map<int, RefVec>::const_iterator const_iterator;
};
-struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
- typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
- typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
+struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
+ typedef hash_map<const Value*, RefVec>:: iterator iterator;
+ typedef hash_map<const Value*, RefVec>::const_iterator const_iterator;
};
//
@@ -636,8 +636,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:
- if (const Instruction* srcI =
- dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
+ if (const Value* srcI = MI.getOperand(i).getVRegValue())
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
@@ -667,8 +666,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
//
for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
- if (const Instruction *srcI =
- dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
+ if (const Value* srcI = MI.getImplicitRef(i))
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
@@ -738,9 +736,9 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
+ assert(mop.getVRegValue() != NULL && "Null value being defined?");
- const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
- valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
+ valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
}
//
@@ -759,10 +757,11 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
continue; // nothing more to do
}
- if (mop.opIsDefOnly() || mop.opIsDefAndUse())
- if (const Instruction* defInstr =
- dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
- valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
+ if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
+ assert(minstr.getImplicitRef(i) != NULL && "Null value being defined?");
+ valueToDefVecMap[minstr.getImplicitRef(i)].push_back(std::make_pair(node,
+ -i));
+ }
}
}
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