Fix typos.

Pointed out by: Sebastian Pop  <sebpop@gmail.com>

llvm-svn: 154337

3 files changed, 4 insertions, 4 deletions

diff --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp
index 464367dd47a..c849fd34359 100644
--- a/polly/lib/Analysis/ScopInfo.cpp
+++ b/polly/lib/Analysis/ScopInfo.cpp
@@ -324,12 +324,12 @@ MemoryAccess::MemoryAccess(const IRAccess &Access, ScopStmt *Statement) {
 
   setBaseName();
 
-  // Devide the access function by the size of the elements in the array.
+  // Divide the access function by the size of the elements in the array.
   //
   // A stride one array access in C expressed as A[i] is expressed in LLVM-IR
   // as something like A[i * elementsize]. This hides the fact that two
   // subsequent values of 'i' index two values that are stored next to each
-  // other in memory. By this devision we make this characteristic obvious
+  // other in memory. By this division we make this characteristic obvious
   // again.
   isl_int v;
   isl_int_init(v);
diff --git a/polly/lib/ScheduleOptimizer.cpp b/polly/lib/ScheduleOptimizer.cpp
index f938bea21cb..01630aa3280 100644
--- a/polly/lib/ScheduleOptimizer.cpp
+++ b/polly/lib/ScheduleOptimizer.cpp
@@ -291,7 +291,7 @@ isl_union_map *getScheduleForBand(isl_band *Band, int *Dimensions) {
 //
 // This transformation creates a loop at the innermost level. The loop has a
 // constant number of iterations, if the number of loop iterations at
-// DimToVectorize can be devided by VectorWidth. The default VectorWidth is
+// DimToVectorize can be divided by VectorWidth. The default VectorWidth is
 // currently constant and not yet target specific. This function does not reason
 // about parallelism.
 static isl_map *getPrevectorMap(isl_ctx *ctx, int DimToVectorize,
diff --git a/polly/lib/Support/SCEVValidator.cpp b/polly/lib/Support/SCEVValidator.cpp
index a70cf1a3384..580191fc8e3 100644
--- a/polly/lib/Support/SCEVValidator.cpp
+++ b/polly/lib/Support/SCEVValidator.cpp
@@ -213,7 +213,7 @@ public:
     ValidatorResult LHS = visit(Expr->getLHS());
     ValidatorResult RHS = visit(Expr->getRHS());
 
-    // We currently do not represent an unsigned devision as an affine
+    // We currently do not represent an unsigned division as an affine
     // expression. If the division is constant during Scop execution we treat it
     // as a parameter, otherwise we bail out.
     if (LHS.isConstant() && RHS.isConstant())