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| author | Craig Topper <craig.topper@intel.com> | 2017-10-28 05:52:23 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-28 05:52:23 +0000 |
| commit | f8b92661b8959cd015d9904b167c010749c2b0d7 (patch) | |
| tree | e23e8d274b7f574068432e613e9d38204555dec3 | |
| parent | eb92e569dedf2b21fa742b5976d34da06b6022c7 (diff) | |
| download | bcm5719-llvm-f8b92661b8959cd015d9904b167c010749c2b0d7.tar.gz bcm5719-llvm-f8b92661b8959cd015d9904b167c010749c2b0d7.zip | |
[X86] Remove unneeded MVT::i1 related code from fast isel.
llvm-svn: 316825
| -rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 9c81be1622a..32f03998a60 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -3512,16 +3512,6 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) { report_fatal_error("SSE register return with SSE disabled"); } - // If the return value is an i1 and AVX-512 is enabled, we need - // to do a fixup to make the copy legal. - if (CopyVT == MVT::i1 && SrcReg == X86::AL && Subtarget->hasAVX512()) { - // Need to copy to a GR32 first. - // TODO: MOVZX isn't great here. We don't care about the upper bits. - SrcReg = createResultReg(&X86::GR32RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(X86::MOVZX32rr8), SrcReg).addReg(X86::AL); - } - // If we prefer to use the value in xmm registers, copy it out as f80 and // use a truncate to move it from fp stack reg to xmm reg. if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) && |
