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authorCraig Topper <craig.topper@gmail.com>2015-12-27 06:55:08 +0000
committerCraig Topper <craig.topper@gmail.com>2015-12-27 06:55:08 +0000
commitf8423c05ee577d5aefce1dc95cb36e0ef12a2fd1 (patch)
treea0c21dda3da86f6343fc409e36740d7519a45d3c
parent904895f0ff7079a0d54325a16893cd33bbda102e (diff)
downloadbcm5719-llvm-f8423c05ee577d5aefce1dc95cb36e0ef12a2fd1.tar.gz
bcm5719-llvm-f8423c05ee577d5aefce1dc95cb36e0ef12a2fd1.zip
[AVX-512] Remove alernate integer forms for VPERMILPS and VPERMILPD. There no tests for them and I don't see any way to select them anyway. If they are really needed they should be implemented as patterns and not full fledged instructions.
llvm-svn: 256462
-rw-r--r--llvm/lib/Target/X86/X86InstrAVX512.td8
1 files changed, 0 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index f7e5d9c7b52..59a8ead8c6e 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -4299,14 +4299,6 @@ multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
X86VPermilpi, _>,
EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
-
- let isCodeGenOnly = 1 in {
- // lowering implementation with the alternative types
- defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
- defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
- OpcodeStr, X86VPermilpi, Ctrl>,
- EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
- }
}
defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
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