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authorTom Stellard <thomas.stellard@amd.com>2014-07-21 17:12:40 +0000
committerTom Stellard <thomas.stellard@amd.com>2014-07-21 17:12:40 +0000
commitf757b5ddc24486639a87bcbb86c56ae9832a9be3 (patch)
tree209fd8fc6649fddb486c42d7f03f185690cbe5b3
parentca000c6c7b2c20334b5e22e40d9fd148ec227c99 (diff)
downloadbcm5719-llvm-f757b5ddc24486639a87bcbb86c56ae9832a9be3.tar.gz
bcm5719-llvm-f757b5ddc24486639a87bcbb86c56ae9832a9be3.zip
R600/SI: Initailize encoding fields of unused VOP3 modifiers to 0
llvm-svn: 213564
-rw-r--r--llvm/lib/Target/R600/SIInstrInfo.td5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td
index 8c1da6c9164..f3517035f35 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.td
+++ b/llvm/lib/Target/R600/SIInstrInfo.td
@@ -316,7 +316,9 @@ multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
opName#"_e64 $dst, $src0_modifiers, $clamp, $omod", []
>, VOP <opName> {
let src1 = 0;
+ let src1_modifiers = 0;
let src2 = 0;
+ let src2_modifiers = 0;
}
}
@@ -348,6 +350,7 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", []
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
let src2 = 0;
+ let src2_modifiers = 0;
}
}
@@ -376,6 +379,7 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", []
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
let src2 = 0;
+ let src2_modifiers = 0;
/* the VOP2 variant puts the carry out into VCC, the VOP3 variant
can write it into any SGPR. We currently don't use the carry out,
so for now hardcode it to VCC as well */
@@ -440,6 +444,7 @@ class VOP3_64_32 <bits <9> op, string opName, list<dag> pattern> : VOP3 <
>, VOP <opName> {
let src2 = 0;
+ let src2_modifiers = 0;
let src0_modifiers = 0;
let clamp = 0;
let omod = 0;
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