[GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode.

A majority of loads and stores at O0 access an alloca.

It's trivial to fold the G_FRAME_INDEX into the instruction; do it.

llvm-svn: 298864

3 files changed, 71 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index be0f6eb44d1..70c11c125ef 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -792,6 +792,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
       }
     }
 
+    // If we haven't folded anything into our addressing mode yet, try to fold
+    // a frame index into the base+offset.
+    if (!Offset && PtrMI->getOpcode() == TargetOpcode::G_FRAME_INDEX)
+      I.getOperand(1).ChangeToFrameIndex(PtrMI->getOperand(1).getIndex());
+
     I.addOperand(MachineOperand::CreateImm(Offset));
 
     // If we're storing a 0, use WZR/XZR.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
index 09b40201f9a..9188e2b0c0f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -8,6 +8,11 @@
   define void @load_s16_gpr(i16* %addr) { ret void }
   define void @load_s8_gpr(i8* %addr) { ret void }
 
+  define void @load_fi_s64_gpr() {
+    %ptr0 = alloca i64
+    ret void
+  }
+
   define void @load_gep_128_s64_gpr(i64* %addr) { ret void }
   define void @load_gep_512_s32_gpr(i32* %addr) { ret void }
   define void @load_gep_64_s16_gpr(i16* %addr) { ret void }
@@ -126,6 +131,34 @@ body:             |
 ...
 
 ---
+# CHECK-LABEL: name: load_fi_s64_gpr
+name:            load_fi_s64_gpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+stack:
+  - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+
+# CHECK:  body:
+# CHECK: %1 = LDRXui %stack.0.ptr0, 0 :: (load 8)
+# CHECK: %x0 = COPY %1
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0(p0) = G_FRAME_INDEX %stack.0.ptr0
+    %1(s64) = G_LOAD %0 :: (load 8)
+    %x0 = COPY %1(s64)
+...
+
+---
 # CHECK-LABEL: name: load_gep_128_s64_gpr
 name:            load_gep_128_s64_gpr
 legalized:       true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
index d40a1231df2..9b8f5c566ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -11,6 +11,11 @@
   define void @store_zero_s64_gpr(i64* %addr) { ret void }
   define void @store_zero_s32_gpr(i32* %addr) { ret void }
 
+  define void @store_fi_s64_gpr() {
+    %ptr0 = alloca i64
+    ret void
+  }
+
   define void @store_gep_128_s64_gpr(i64* %addr) { ret void }
   define void @store_gep_512_s32_gpr(i32* %addr) { ret void }
   define void @store_gep_64_s16_gpr(i16* %addr) { ret void }
@@ -184,6 +189,34 @@ body:             |
 ...
 
 ---
+# CHECK-LABEL: name: store_fi_s64_gpr
+name:            store_fi_s64_gpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+stack:
+  - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+
+# CHECK:  body:
+# CHECK: %0 = COPY %x0
+# CHECK: STRXui %0, %stack.0.ptr0, 0 :: (store 8)
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0(p0) = COPY %x0
+    %1(p0) = G_FRAME_INDEX %stack.0.ptr0
+    G_STORE  %0, %1 :: (store 8)
+...
+
+---
 # CHECK-LABEL: name: store_gep_128_s64_gpr
 name:            store_gep_128_s64_gpr
 legalized:       true