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| author | Amara Emerson <aemerson@apple.com> | 2019-09-25 04:52:42 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-09-25 04:52:42 +0000 |
| commit | f674d7dab1b17c7e8b1f37ce06345760f94d2ede (patch) | |
| tree | 924a61f868e2ac37602b8cd4005b43740e2c80b8 | |
| parent | a18b00c8d593f147f598ca21dff6f79c314d1133 (diff) | |
| download | bcm5719-llvm-f674d7dab1b17c7e8b1f37ce06345760f94d2ede.tar.gz bcm5719-llvm-f674d7dab1b17c7e8b1f37ce06345760f94d2ede.zip | |
[AArch64][GlobalISel] Tweak legalization rule for G_BSWAP to handle widening s16.
llvm-svn: 372812
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir | 44 |
2 files changed, 45 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 7ff7902f1e0..7a1901bd5b1 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -82,7 +82,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { getActionDefinitionsBuilder(G_BSWAP) .legalFor({s32, s64, v4s32, v2s32, v2s64}) - .clampScalar(0, s16, s64) + .clampScalar(0, s32, s64) .widenScalarToNextPow2(0); getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir new file mode 100644 index 00000000000..5e5cbf63bb0 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s +--- | + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64" + + declare i16 @llvm.bswap.i16(i16) #0 + + define i16 @bswap_s16(i16 %a) { ret i16 0 } + + attributes #0 = { nounwind readnone speculatable willreturn } + +... +--- +name: bswap_s16 +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$w0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.1: + liveins: $w0 + + ; CHECK-LABEL: name: bswap_s16 + ; CHECK: liveins: $w0 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]] + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64) + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) + ; CHECK: $w0 = COPY [[COPY2]](s32) + ; CHECK: RET_ReallyLR implicit $w0 + %1:_(s32) = COPY $w0 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_BSWAP %0 + %3:_(s32) = G_ANYEXT %2(s16) + $w0 = COPY %3(s32) + RET_ReallyLR implicit $w0 + +... |
