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author | Craig Topper <craig.topper@gmail.com> | 2014-03-09 07:58:15 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2014-03-09 07:58:15 +0000 |
commit | f5e3b0b98c131c508cf0604982952f9804fe74df (patch) | |
tree | b08ecb668ef2bb1c9b188b7713e397b75f52cf94 | |
parent | 2d9361e325e2a99edd0522f37f4555bd59ef6ac3 (diff) | |
download | bcm5719-llvm-f5e3b0b98c131c508cf0604982952f9804fe74df.tar.gz bcm5719-llvm-f5e3b0b98c131c508cf0604982952f9804fe74df.zip |
De-virtualize some methods since they don't override anything.
llvm-svn: 203379
-rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 2069e57ff26..a02db038f8c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -161,7 +161,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } + const X86RegisterInfo &getRegisterInfo() const { return RI; } /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" /// extension instruction. That is, it's like a copy where it's legal for the @@ -257,12 +257,12 @@ public: const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - MachineInstr::mmo_iterator MMOBegin, - MachineInstr::mmo_iterator MMOEnd, - SmallVectorImpl<MachineInstr*> &NewMIs) const; + void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + MachineInstr::mmo_iterator MMOBegin, + MachineInstr::mmo_iterator MMOEnd, + SmallVectorImpl<MachineInstr*> &NewMIs) const; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, @@ -270,12 +270,12 @@ public: const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - MachineInstr::mmo_iterator MMOBegin, - MachineInstr::mmo_iterator MMOEnd, - SmallVectorImpl<MachineInstr*> &NewMIs) const; + void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + MachineInstr::mmo_iterator MMOBegin, + MachineInstr::mmo_iterator MMOEnd, + SmallVectorImpl<MachineInstr*> &NewMIs) const; bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; |