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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-16 00:20:54 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-16 00:20:54 +0000 |
| commit | f5d5cd205e7bc5177c80d39c03eac26eff916d20 (patch) | |
| tree | 5268876f63feabad144191c79807ed92d159692a | |
| parent | 431141c5cc343c7601cbd5f30c5b34810b123e5c (diff) | |
| download | bcm5719-llvm-f5d5cd205e7bc5177c80d39c03eac26eff916d20.tar.gz bcm5719-llvm-f5d5cd205e7bc5177c80d39c03eac26eff916d20.zip | |
AMDGPU/GlobalISel: Fix VALU s16 fneg
llvm-svn: 371948
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 20 |
2 files changed, 19 insertions, 11 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index a99977d72d9..52254750f60 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1109,6 +1109,11 @@ def : GCNPat < >; def : GCNPat < + (fneg (f16 VGPR_32:$src)), + (V_XOR_B32_e32 (S_MOV_B32 (i32 0x00008000)), VGPR_32:$src) +>; + +def : GCNPat < (fabs (f16 SReg_32:$src)), (S_AND_B32 SReg_32:$src, (S_MOV_B32 (i32 0x00007fff))) >; @@ -1119,6 +1124,11 @@ def : GCNPat < >; def : GCNPat < + (fneg (fabs (f16 VGPR_32:$src))), + (V_OR_B32_e32 (S_MOV_B32 (i32 0x00008000)), VGPR_32:$src) // Set sign bit +>; + +def : GCNPat < (fneg (v2f16 SReg_32:$src)), (S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000))) >; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir index ed0109e1f5b..9395b0c8653 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir @@ -95,11 +95,10 @@ body: | liveins: $vgpr0 ; GCN-LABEL: name: fneg_s16_vv ; GCN: liveins: $vgpr0 - ; GCN: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GCN: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) - ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]] - ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16) - ; GCN: $vgpr0 = COPY [[COPY1]](s32) + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 + ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec + ; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]] %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_FNEG %1 @@ -349,12 +348,11 @@ body: | liveins: $vgpr0 ; GCN-LABEL: name: fneg_fabs_s16_vv ; GCN: liveins: $vgpr0 - ; GCN: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GCN: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) - ; GCN: [[FABS:%[0-9]+]]:vgpr(s16) = G_FABS [[TRUNC]] - ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FABS]] - ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0(s32) = COPY [[FNEG]](s16) - ; GCN: $vgpr0 = COPY [[COPY1]](s32) + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 + ; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec + ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[V_OR_B32_e32_]] + ; GCN: $vgpr0 = COPY [[COPY1]] %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_FABS %1 |
