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| author | Andrew Lenharth <andrewl@lenharth.org> | 2008-03-01 22:27:48 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2008-03-01 22:27:48 +0000 |
| commit | f5c90ec12c669f7e9a9ace2f38e3fe39bd03e0ad (patch) | |
| tree | c85d3d8ee00905985346b3289afda9b2b7c6625d | |
| parent | d032c33300fd6915e59f06a478f3d38ace39957a (diff) | |
| download | bcm5719-llvm-f5c90ec12c669f7e9a9ace2f38e3fe39bd03e0ad.tar.gz bcm5719-llvm-f5c90ec12c669f7e9a9ace2f38e3fe39bd03e0ad.zip | |
make CAS work
llvm-svn: 47799
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4cb94916138..6c7f5fede6f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -5358,10 +5358,10 @@ SDOperand X86TargetLowering::LowerCAS(SDOperand Op, SelectionDAG &DAG) { case MVT::i32: Reg = X86::EAX; size = 4; break; }; SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, - Op.getOperand(2), SDOperand()); + Op.getOperand(3), SDOperand()); SDOperand Ops[] = { cpIn.getValue(0), Op.getOperand(1), - Op.getOperand(3), + Op.getOperand(2), DAG.getTargetConstant(size, MVT::i8), cpIn.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index a109dc64887..134aeb63d11 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2548,6 +2548,7 @@ def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), //FIXME: Please check the format Pseudo is certainly wrong, but the opcode and // prefixes should be correct + let Defs = [EAX, EFLAGS], Uses = [EAX] in { def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap), "cmpxchgl $swap,$ptr", []>, TB; |
