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authorThomas Lively <tlively@google.com>2019-03-02 00:18:07 +0000
committerThomas Lively <tlively@google.com>2019-03-02 00:18:07 +0000
commitf5a8c28e7e28e0969e7e9608487ab5a061379393 (patch)
treeabaf81098adf9b35761832043acc9b775af561df
parentba4538708a52469dcb09933581102078821612e6 (diff)
downloadbcm5719-llvm-f5a8c28e7e28e0969e7e9608487ab5a061379393.tar.gz
bcm5719-llvm-f5a8c28e7e28e0969e7e9608487ab5a061379393.zip
[WebAssembly][WIP] Expand operations not supported by SIMD
llvm-svn: 355247
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp17
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 50bd5a94f4b..d79e32d9e9b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -174,6 +174,23 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
setOperationAction(Op, T, Expand);
}
+ // Expand integer operations supported for scalars but not SIMD
+ for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
+ ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
+ for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+ setOperationAction(Op, T, Expand);
+ if (Subtarget->hasUnimplementedSIMD128())
+ setOperationAction(Op, MVT::v2i64, Expand);
+ }
+
+ // Expand float operations supported for scalars but not SIMD
+ for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
+ ISD::FCOPYSIGN}) {
+ setOperationAction(Op, MVT::v4f32, Expand);
+ if (Subtarget->hasUnimplementedSIMD128())
+ setOperationAction(Op, MVT::v2f32, Expand);
+ }
+
// Expand additional SIMD ops that V8 hasn't implemented yet
if (!Subtarget->hasUnimplementedSIMD128()) {
setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
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