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| author | Jessica Paquette <jpaquette@apple.com> | 2019-04-25 20:00:57 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2019-04-25 20:00:57 +0000 |
| commit | f54258c88842dccf6d63c09e395e5889267c1836 (patch) | |
| tree | b748234889f7878fc75f0ae691c849611563f0f7 | |
| parent | f46c58e0c610bba6c8fa075462f68d94e28c676c (diff) | |
| download | bcm5719-llvm-f54258c88842dccf6d63c09e395e5889267c1836.tar.gz bcm5719-llvm-f54258c88842dccf6d63c09e395e5889267c1836.zip | |
[GlobalISel][AArch64] Make G_EXTRACT_VECTOR_ELT legal for v8s16s
This case was missing before, so we couldn't legalize it.
Add it to AArch64LegalizerInfo.cpp and update select-extract-vector-elt.mir.
llvm-svn: 359231
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir | 23 |
2 files changed, 25 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 508290c2800..01661fbdaeb 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -517,8 +517,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { .minScalar(2, s64) .legalIf([=](const LegalityQuery &Query) { const LLT &VecTy = Query.Types[1]; - return VecTy == v2s16 || VecTy == v4s16 || VecTy == v4s32 || - VecTy == v2s64 || VecTy == v2s32; + return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 || + VecTy == v4s32 || VecTy == v2s64 || VecTy == v2s32; }); getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir index 4a25670bc12..f285ca75813 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir @@ -115,3 +115,26 @@ body: | RET_ReallyLR implicit $h0 ... +--- +name: v8s16_fpr +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: v8s16_fpr + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 + ; CHECK: $h0 = COPY [[CPYi16_]] + ; CHECK: RET_ReallyLR implicit $h0 + %0:fpr(<8 x s16>) = COPY $q0 + %2:gpr(s64) = G_CONSTANT i64 1 + %3:fpr(s64) = COPY %2(s64) + %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64) + $h0 = COPY %1(s16) + RET_ReallyLR implicit $h0 + +... |
