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authorJim Grosbach <grosbach@apple.com>2011-08-12 21:02:34 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-12 21:02:34 +0000
commitf402f694e297f4f8e148ee8197d2aa90e5ba782e (patch)
treeee9835ada42a809378f3e8cf27af7e2908730b2c
parent94f8c779314c50601c5dc66ded879515798b8bf1 (diff)
downloadbcm5719-llvm-f402f694e297f4f8e148ee8197d2aa90e5ba782e.tar.gz
bcm5719-llvm-f402f694e297f4f8e148ee8197d2aa90e5ba782e.zip
ARM expansion of pre-indexed store pseudos should maintain memoperands.
Partial fix for rdar://9945172. llvm-svn: 137513
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index abec1aa50ef..c6fc3237873 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5300,13 +5300,15 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
if (isSub)
Offset = -Offset;
+ MachineMemOperand *MMO = *MI->memoperands_begin();
MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc))
.addOperand(MI->getOperand(0)) // Rn_wb
.addOperand(MI->getOperand(1)) // Rt
.addOperand(MI->getOperand(2)) // Rn
.addImm(Offset) // offset (skip GPR==zero_reg)
.addOperand(MI->getOperand(5)) // pred
- .addOperand(MI->getOperand(6));
+ .addOperand(MI->getOperand(6))
+ .addMemOperand(MMO);
MI->eraseFromParent();
return BB;
}
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