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| author | Craig Topper <craig.topper@intel.com> | 2018-02-15 20:27:30 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-15 20:27:30 +0000 |
| commit | f3f35efe5c911e7dd51c58a92b073806a8909a3a (patch) | |
| tree | 202bf8ae0f337228a247b5f976a22544f17b6145 | |
| parent | dac3c1f5c8547f17df9c0300e40937015c9216ad (diff) | |
| download | bcm5719-llvm-f3f35efe5c911e7dd51c58a92b073806a8909a3a.tar.gz bcm5719-llvm-f3f35efe5c911e7dd51c58a92b073806a8909a3a.zip | |
[X86] Enable BT to be used in place of TEST for single bit checks under optsize
We already do this for 64-bit when it won't fit into a 64-bit AND/TEST's immediate field. This adds an additional qualifier to do it for any single bit constant larger than 8-bits under optsize
Differential Revision: https://reviews.llvm.org/D43346
llvm-svn: 325290
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 15 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/test-vs-bittest.ll | 12 |
2 files changed, 15 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9a1f2405e7d..66315b5af11 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17709,12 +17709,15 @@ static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC, if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { LHS = AndLHS.getOperand(0); RHS = AndLHS.getOperand(1); - } - - // Use BT if the immediate can't be encoded in a TEST instruction. - if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { - LHS = AndLHS; - RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType()); + } else { + // Use BT if the immediate can't be encoded in a TEST instruction or we + // are optimizing for size and the immedaite won't fit in a byte. + bool OptForSize = DAG.getMachineFunction().getFunction().optForSize(); + if ((!isUInt<32>(AndRHSVal) || (OptForSize && !isUInt<8>(AndRHSVal))) && + isPowerOf2_64(AndRHSVal)) { + LHS = AndLHS; + RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType()); + } } } diff --git a/llvm/test/CodeGen/X86/test-vs-bittest.ll b/llvm/test/CodeGen/X86/test-vs-bittest.ll index 999c2224c4d..44f77e8b7ce 100644 --- a/llvm/test/CodeGen/X86/test-vs-bittest.ll +++ b/llvm/test/CodeGen/X86/test-vs-bittest.ll @@ -75,8 +75,8 @@ define void @test64_optsize_2(i64 inreg %x) optsize { ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: testl $2048, %edi # imm = 0x800 -; CHECK-NEXT: je .LBB3_2 +; CHECK-NEXT: btl $11, %edi +; CHECK-NEXT: jae .LBB3_2 ; CHECK-NEXT: # %bb.1: # %yes ; CHECK-NEXT: callq bar ; CHECK-NEXT: .LBB3_2: # %no @@ -259,8 +259,8 @@ define void @test32_optsize_2(i32 inreg %x) optsize { ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: testl $2048, %edi # imm = 0x800 -; CHECK-NEXT: je .LBB11_2 +; CHECK-NEXT: btl $11, %edi +; CHECK-NEXT: jae .LBB11_2 ; CHECK-NEXT: # %bb.1: # %yes ; CHECK-NEXT: callq bar ; CHECK-NEXT: .LBB11_2: # %no @@ -351,8 +351,8 @@ define void @test16_optsize_2(i16 inreg %x) optsize { ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: testl $2048, %edi # imm = 0x800 -; CHECK-NEXT: je .LBB15_2 +; CHECK-NEXT: btl $11, %edi +; CHECK-NEXT: jae .LBB15_2 ; CHECK-NEXT: # %bb.1: # %yes ; CHECK-NEXT: callq bar ; CHECK-NEXT: .LBB15_2: # %no |
