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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-07-30 12:16:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-07-30 12:16:47 +0000 |
| commit | f3c9a34def73e18eaa97ae7c43fd12a80fd405be (patch) | |
| tree | b63858ec6ba7712cd00488472570320fae998348 | |
| parent | cd73fe8989781a390131a84d61f662894181dcf8 (diff) | |
| download | bcm5719-llvm-f3c9a34def73e18eaa97ae7c43fd12a80fd405be.tar.gz bcm5719-llvm-f3c9a34def73e18eaa97ae7c43fd12a80fd405be.zip | |
AMDGPU: Make fneg combine handle fcanonicalize
llvm-svn: 338243
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 21 |
2 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 002ee7fcc72..21e44e9589d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -554,6 +554,7 @@ static bool fnegFoldsIntoOp(unsigned Opc) { case ISD::FTRUNC: case ISD::FRINT: case ISD::FNEARBYINT: + case ISD::FCANONICALIZE: case AMDGPUISD::RCP: case AMDGPUISD::RCP_LEGACY: case AMDGPUISD::RCP_IFLAG: @@ -3595,6 +3596,7 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, case ISD::FRINT: case ISD::FNEARBYINT: // XXX - Should fround be handled? case ISD::FSIN: + case ISD::FCANONICALIZE: case AMDGPUISD::RCP: case AMDGPUISD::RCP_LEGACY: case AMDGPUISD::RCP_IFLAG: diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll index fd3d4f053e9..520309e0a9f 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll @@ -1725,6 +1725,26 @@ define amdgpu_kernel void @v_fneg_nearbyint_f32(float addrspace(1)* %out, float } ; -------------------------------------------------------------------------------- +; fcanonicalize tests +; -------------------------------------------------------------------------------- + +; GCN-LABEL: {{^}}v_fneg_canonicalize_f32: +; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] +; GCN: v_mul_f32_e64 [[RESULT:v[0-9]+]], 1.0, -[[A]] +; GCN: buffer_store_dword [[RESULT]] +define amdgpu_kernel void @v_fneg_canonicalize_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext + %a = load volatile float, float addrspace(1)* %a.gep + %trunc = call float @llvm.canonicalize.f32(float %a) + %fneg = fsub float -0.0, %trunc + store float %fneg, float addrspace(1)* %out.gep + ret void +} + +; -------------------------------------------------------------------------------- ; vintrp tests ; -------------------------------------------------------------------------------- @@ -2117,6 +2137,7 @@ declare float @llvm.trunc.f32(float) #1 declare float @llvm.round.f32(float) #1 declare float @llvm.rint.f32(float) #1 declare float @llvm.nearbyint.f32(float) #1 +declare float @llvm.canonicalize.f32(float) #1 declare float @llvm.minnum.f32(float, float) #1 declare float @llvm.maxnum.f32(float, float) #1 |
